A Semantic Approach for Modular Synthesis of VLSI Systems. - M. Balakrishnan; S. Sutarwala; Arun K. Majumdar; Dilip K. Banerji; James G. Linders (Inf. Process. Lett., 1988)

TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. - Rolf Ernst; S. Sutarwala; J.-Y. Jou (ITC, 1989)

Simulation based verification of register-transfer level behavioral synthesis tools. - Rolf Ernst; S. Sutarwala; J.-Y. Jou; M. Tong (EURO-DAC, 1990)