A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. - Varna Puvvada; S. Potla; S. Tamizh Selvam; P. R. Suresh (VLSI Design, 1995)

Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. - R. P. Suresh; P. Venugopal; S. Tamizh Selvam; S. Potla (VLSI Design, 1996)