Design of a Real Time Geometric Classifier. - Michel Robert; Patrick Gorria; Johel Mitéran; S. Turgis (EDAC-ETC-EUROASIC, 1994)

Explicit evaluation of short circuit power dissipation for CMOS logic structures. - S. Turgis; Nadine Azémard; Daniel Auvergne (ISLPD, 1995)

Design and selection of buffers for minimum power-delay product. - S. Turgis; Nadine Azémard; Daniel Auvergne (ED&TC, 1996)

Internal power modelling and minimization in CMOS inverters. - S. Turgis; Jean Michel Daga; Josep M. Portal; Daniel Auvergne (ED&TC, 1997)

A novel macromodel for power estimation in CMOS structures. - S. Turgis; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)