Processor and Link Assignment in Multicomputers Using Simulated Annealing. - S. Wayne Bollinger; Scott F. Midkiff (ICPP (1), 1988)

On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits. - S. Wayne Bollinger; Scott F. Midkiff (ITC, 1991)

Circuit-level classification and testability analysis for CMOS faults. - Scott F. Midkiff; S. Wayne Bollinger (VTS, 1991)

Heuristic Technique for Processor and Link Assignment in Multicomputers. - S. Wayne Bollinger; Scott F. Midkiff (IEEE Trans. Computers, 1991)

An investigation of circuit partitioning for parallel test generation. - S. Wayne Bollinger; Scott F. Midkiff (VTS, 1992)

Classification of bridging faults in CMOS circuits: experimental results and implications for test. - Scott F. Midkiff; S. Wayne Bollinger (VTS, 1993)

Test generation for IDDQ testing of bridging faults in CMOS circuits. - S. Wayne Bollinger; Scott F. Midkiff (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Design planning for high-performance ASICs. - John Y. Sayah; Rajesh Gupta; Deepak D. Sherlekar; Philip S. Honsinger; Jitendra M. Apte; S. Wayne Bollinger; Hai Hsia Chen; Sumit DasGupta; Edward P. Hsieh; Andrew D. Huber; Edward J. Hughes; Zahi M. Kurzum; et al. (IBM J. Res. Dev., 1996)