Global Hardware Synthesis from Behavioral Dataflow Descriptions. - Josef Scheichenzuber; Werner Grass; Ulrich Lauther; Sabine März (DAC, 1990)

Subtype concept of VHDL for synthesis constraints. - Wolfgang Ecker; Sabine März (EURO-DAC, 1992)

System-Level Specification and Design Using VHDL: A Case Study. - Wolfgang Ecker; Sabine März (CHDL, 1993)

The Siemens high-level synthesis system CALLAS. - Jörg Biesenack; Michael Koster; Anton Langmaier; Stephane Ledeux; Sabine März; Michael Payer; Michael Pilsl; Steffen Rumler; Holger Soukup; Norbert Wehn; Peter Duzy (IEEE Trans. Very Large Scale Integr. Syst., 1993)