On the capacity of a noisy continuous channel. - Saburo Muroga (IRE Trans. Inf. Theory, 1957)

The principle of majority decision logical elements and the complexity of their circuits. - Saburo Muroga (IFIP Congress, 1959)

The Parametron Digital Computer MUSASINO-1. - Saburo Muroga; Kensuke Takashima (IRE Trans. Electron. Comput., 1959)

Two problems on threshold functions - Calvin C. Elgot; Saburo Muroga (SWCT, 1961)

Functional forms of majority functions and a necessary and sufficient condition for their realizability - Saburo Muroga (SWCT, 1961)

Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight - Saburo Muroga (SWCT, 1962)

Generation and Asymmetry of Self-Dual Threshold Functions. - Saburo Muroga (IEEE Trans. Electron. Comput., 1965)

Lower Bounds of the Number of Threshold Functions and a Maximum Weight. - Saburo Muroga (IEEE Trans. Electron. Comput., 1965)

Lower Bound of the Number of Threshold Functions. - Saburo Muroga; Iwao Toda (IEEE Trans. Electron. Comput., 1966)

Enumeration of Threshold Functions of Eight Variables. - Saburo Muroga; Teiichi Tsuboi; Charles R. Baugh (IEEE Trans. Computers, 1970)

Adaptive Linear Classifier by Linear Programming. - Toshihide Ibaraki; Saburo Muroga (IEEE Trans. Syst. Sci. Cybern., 1970)

Threshold logic and its applications. - Saburo Muroga (Wiley, 1971)

Technical Note - Results in Using Gomory's All-Integer Integer Algorithm to Design Optimum Logic Networks. - Charles R. Baugh; Toshihide Ibaraki; Saburo Muroga (Oper. Res., 1971)

Synthesis of Networks with a Minimum Number of Negative Gates. - Toshihide Ibaraki; Saburo Muroga (IEEE Trans. Computers, 1971)

An implicit enumeration program for zero-one integer programming. - Toshihide Ibaraki; Tso-Kai Liu; Charles R. Baugh; Saburo Muroga (Int. J. Parallel Program., 1972)

Optimal Networks of NOR-OR Gates for Functions of Three Variables. - Charles R. Baugh; C. S. Chandersekaran; Richard S. Swee; Saburo Muroga (IEEE Trans. Computers, 1972)

Design of Optimal Switching Networks by Integer Programming. - Saburo Muroga; Toshihide Ibaraki (IEEE Trans. Computers, 1972)

Redundancy check technique for designing optimal networks by branch-and-bound method. - Hung Chi Lai; Tomoyasu Nakagawa; Saburo Muroga (Int. J. Parallel Program., 1974)

Optimal One-Bit Full Adders With Different Types of Gates. - Tso-Kai Liu; Keith R. Hohulin; Lih-Er Shiau; Saburo Muroga (IEEE Trans. Computers, 1974)

Minimization of Logic Networks Under a Generalized Cost Function. - Saburo Muroga; Hung Chi Lai (IEEE Trans. Computers, 1976)

Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. - Jay Niel Culliney; Ming Huei Young; Tomoyasu Nakagawa; Saburo Muroga (IEEE Trans. Computers, 1979)

Comments on "Computing Irredundant Normal Forms from Abbreviated Presence Functions". - Robert Brian Cutler; Saburo Muroga (IEEE Trans. Computers, 1979)

Comments on "Generalization of Consensus Theory and Application to the Minimization of Boolean Functions". - Robert Brian Cutler; Saburo Muroga (IEEE Trans. Computers, 1979)

Minimum Parallel Binary Adders with NOR (NAND) Gates. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Computers, 1979)

Useless prime implicants of incompletely specified multiple-output switching functions. - Robert Brian Cutler; Saburo Muroga (Int. J. Parallel Program., 1980)

Logic Networks of Carry-Save Adders. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Computers, 1982)

Parallel Binary Adders with a Minimum Number of Connections. - Akito Sakurai; Saburo Muroga (IEEE Trans. Computers, 1983)

Parallel multipliers with NOR gates based on G-minimum adders. - Ging-Shung Yu; Saburo Muroga (Int. J. Parallel Program., 1984)

Minimal covering problem and PLA minimization. - Ming Huei Young; Saburo Muroga (Int. J. Parallel Program., 1985)

Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. - Ming Huei Young; Saburo Muroga (IEEE Trans. Computers, 1985)

Properties of Wired Logic. - Yahiko Kambayashi; Saburo Muroga (IEEE Trans. Computers, 1986)

Derivation of Minimal Sums for Completely Specified Functions. - Robert Brian Cutler; Saburo Muroga (IEEE Trans. Computers, 1987)

Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Computers, 1987)

Input assignment algorithm for decoded-PLAs with multi-input decoders. - Kuang-Chien Chen; Saburo Muroga (ICCAD, 1988)

Design of MOS networks in single-rail input logic for incompletely specified functions. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

SYLON-DREAM: a multi-level network synthesizer. - Kuang-Chien Chen; Saburo Muroga (ICCAD, 1989)

The Transduction Method-Design of Logic Networks Based on Permissible Functions. - Saburo Muroga; Yahiko Kambayashi; Hung Chi Lai; Jay Niel Culliney (IEEE Trans. Computers, 1989)

Timing Optimization for Multi-Level Combinational Networks. - Kuang-Chien Chen; Saburo Muroga (DAC, 1990)

SYLON-REDUCE: an MOS network optimization algorithms using permissible functions. - Johnson Chan Limqueco; Saburo Muroga (ICCD, 1990)

A Resynthesis Approach for Network Optimization. - Kuang-Chien Chen; Yusuke Matsunaga; Saburo Muroga; Masahiro Fujita (DAC, 1991)

Logic Optimization of MOS Networks. - Johnson Chan Limqueco; Saburo Muroga (DAC, 1991)

Computer-Aided Logic Synthesis for VLSI Chips. - Saburo Muroga (Adv. Comput., 1991)

Absolute Minimization of Completely Specified Switching Functions. - Sung Je Hong; Saburo Muroga (IEEE Trans. Computers, 1991)

A Shared Memory Parallel Algorithm for Logic Synthesis. - Chieng-Fai Lim; Prithviraj Banerjee; Kaushik De; Saburo Muroga (VLSI Design, 1993)

Optimization methods for lookup-table-based FPGAs using transduction method. - Shigeru Yamashita; Yahiko Kambayashi; Saburo Muroga (ASP-DAC, 1995)

Design of logic circuits with wired-logic utilizing transduction method. - Shigeru Yamashita; Yahiko Kambayashi; Saburo Muroga (Syst. Comput. Jpn., 1996)

Optimization methods for look-up table-type FPGAs based on permissible functions. - Shigeru Yamashita; Yahiko Kambayashi; Saburo Muroga (Syst. Comput. Jpn., 1996)

Binary Decision Diagrams. - Shin-ichi Minato; Saburo Muroga (The VLSI Handbook, 1999)

Expressions of Logic Functions. - Saburo Muroga (The VLSI Handbook, 1999)

Basic Theory of Logic Functions. - Saburo Muroga (The VLSI Handbook, 1999)

Simplification of Logic Expressions. - Saburo Muroga (The VLSI Handbook, 1999)

Logic Synthesis with AND and OR Gates in Two Levels. - Saburo Muroga (The VLSI Handbook, 1999)

Sequential Networks with AND and OR Gates. - Saburo Muroga (The VLSI Handbook, 1999)

Logic Properties of Transistor Circuits. - Saburo Muroga (The VLSI Handbook, 1999)

Logic Synthesis with NAND (or NOR) Gates in Multi-levels. - Saburo Muroga (The VLSI Handbook, 1999)

Logic Synthesis with a Minimum Number of Negative Gates. - Saburo Muroga (The VLSI Handbook, 1999)

Logic Synthesizer by the Transduction Method. - Saburo Muroga (The VLSI Handbook, 1999)

Emitter-Coupled Logic. - Saburo Muroga (The VLSI Handbook, 1999)

CMOS. - Saburo Muroga (The VLSI Handbook, 1999)

Full-Custom and Semi-Custom Design. - Saburo Muroga (The VLSI Handbook, 1999)

Programmable Logic Devices. - Saburo Muroga (The VLSI Handbook, 1999)

Mask-Programmable Gate Arrays. - Saburo Muroga (The VLSI Handbook, 1999)

Field-Programmable Gate Arrays. - Saburo Muroga (The VLSI Handbook, 1999)

Cell-Library Design Approach. - Saburo Muroga (The VLSI Handbook, 1999)

Field-Programmable Gate Arrays. - Saburo Muroga (The VLSI Handbook, 1999)

Logic Synthesis with AND and OR Gates in Multi-levels. - Yuichi Nakamura 003; Saburo Muroga (The VLSI Handbook, 1999)

Multipliers. - Naofumi Takagi; Charles R. Baugh; Saburo Muroga (The VLSI Handbook, 1999)

Dividers. - Naofumi Takagi; Saburo Muroga (The VLSI Handbook, 1999)

Adders. - Naofumi Takagi; Haruyuki Tago; Charles R. Baugh; Saburo Muroga (The VLSI Handbook, 1999)

Pass Transistors. - Kazuo Yano; Saburo Muroga (The VLSI Handbook, 1999)

Logic Synthesizer with Optimizations in Two Phases. - Ko Yoshikawa; Saburo Muroga (The VLSI Handbook, 1999)