A regularity-driven fast gridless detailed router for high frequency datapath designs. - Sabyasachi Das; Sunil P. Khatri (ISPD, 2001)

An efficient and regular routing methodology for datapath designsusing net regularity extraction. - Sabyasachi Das; Sunil P. Khatri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

23mm2 single-chip 0.18μm CMOS GPS receiver with 28mW-4.1 mm2 radio and CPU/DSP/RAM/ROM. - Giuseppe Gramegna; Massimo Franciotta; Valentina Mandará; Nino G. Bellantone; Michele Vaiana; Mario Paparo; Marco Losi; Sabyasachi Das; Philip G. Mattos (CICC, 2004)

Trends in Codon and Amino Acid Usage in Human Pathogen Tropheryma Whipplei, the only Known Actinobacteria with Reduced Genome. - Sabyasachi Das; Sandip Paul; Chitra Dutta (APBC, 2006)

Consequences of Mutation, Selection, and Physico-Chemical Properties of Encoded Proteins on Synonymous Codon Usage in Adenoviruses. - Sandip Paul; Sabyasachi Das; Chitra Dutta (APBC, 2006)

A 56-mW 23-mm2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm2 radio. - Giuseppe Gramegna; Philip G. Mattos; Marco Losi; Sabyasachi Das; Massimo Franciotta; Nino G. Bellantone; Michele Vaiana; Valentina Mandará; Mario Paparo (IEEE J. Solid State Circuits, 2006)

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. - Sabyasachi Das; Sunil P. Khatri (VLSI Design, 2008)

A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. - Sabyasachi Das; Sunil P. Khatri (VLSI Design, 2008)

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. - Sabyasachi Das; Sunil P. Khatri (VLSI Design, 2008)

A Timing-Driven Approach to Synthesize Fast Barrel Shifters. - Sabyasachi Das; Sunil P. Khatri (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Resource sharing among mutually exclusive sum-of-product blocks for area reduction. - Sabyasachi Das; Sunil P. Khatri (ACM Trans. Design Autom. Electr. Syst., 2008)

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. - Sabyasachi Das; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Pseudo-BIST: A Novel Technique for SAR-ADC Testing. - Yatharth Gupta; Sujay Deb; Vikrant Singh; V. N. Srinivasan; Manish Sharma; Sabyasachi Das (VDAT, 2017)