A Fast Algorithm for the Principle Partition of a Graph. - Sachin B. Patkar; H. Narayanan (FSTTCS, 1991)

Fast Sequential and Randomised Parallel Algorithms for Rigidity and approximate Min k-cut. - Sachin B. Patkar; H. Narayanan (FSTTCS, 1992)

Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity. - Sachin B. Patkar; H. Narayanan (ISAAC, 1992)

Abstract and Generic Rigidity in the Plane. - Sachin B. Patkar; Brigitte Servatius; K. V. Subrahmanyam 001 (J. Comb. Theory B, 1994)

Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach. - H. Narayanan; Subir K. Roy; Sachin B. Patkar (J. Algorithms, 1996)

A New Partitioning Strategy Based on Supermodular Functions. - Sachin B. Patkar; Shabbir H. Batterywala; M. Chandramouli; H. Narayanan (VLSI Design, 1997)

Priority Scheduling in Parallel I/O Systems. - C. R. Venugopal; S. S. S. P. Rao; Sachin B. Patkar (PDPTA, 1999)

Realization of set functions as cut functions of graphs and hypergraphs. - Satoru Fujishige; Sachin B. Patkar (Discret. Math., 2001)

A note on optimal covering augmentation for graphic polymatroids. - Sachin B. Patkar; H. Narayanan (Inf. Process. Lett., 2001)

An Efficient Practical Heuristic For Good Ratio-Cut Partitioning. - Sachin B. Patkar; H. Narayanan (VLSI Design, 2003)

The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. - Madhav P. Desai; H. Narayanan; Sachin B. Patkar (Discret. Appl. Math., 2003)

Improving graph partitions using submodular functions. - Sachin B. Patkar; H. Narayanan (Discret. Appl. Math., 2003)

Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and its Connections with Principal Partition. - Sachin B. Patkar; H. Narayanan (J. Comb. Optim., 2003)

Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid. - Janak Porwal; Sachin B. Patkar (ERSA, 2005)

Acceleration of conjugate gradient method for circuit simulation using CUDA. - Anirudh Maringanti; Viraj Athavale; Sachin B. Patkar (HiPC, 2009)

A Pipelined Simulation Approach for Logic Emulation using Multi-FPGA Platforms. - Dinesh Baviskar; Sachin B. Patkar (ISCAS, 2009)

Exploiting Hybrid Analysis in Solving Electrical Networks. - V. Siva Sankar; H. Narayanan; Sachin B. Patkar (VLSI Design, 2009)

Large Scale VLSI Circuit Simulation Using Point Relaxation. - Subhendu Roy; Yogesh Dilip Save; H. Narayanan; Sachin B. Patkar (CSC, 2010)

FPGA Based High Performance Double-Precision Matrix Multiplication. - Vinay B. Y. Kumar; Siddharth Joshi 005; Sachin B. Patkar; H. Narayanan (Int. J. Parallel Program., 2010)

Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA. - Sumedh Attarde; Siddharth Joshi 005; Yash Deshpande; Sunil Puranik; Sachin B. Patkar (PECCS, 2011)

Solution of Partial Differential Equations by electrical analogy. - Yogesh Dilip Save; H. Narayanan; Sachin B. Patkar (J. Comput. Sci., 2011)

FPGA Implementation of Particle Filter Based Object Tracking in Video. - Sumeet Agrawal; Pinal Engineer; Rajbabu Velmurugan; Sachin B. Patkar (ISED, 2012)

Two Graph Based Circuit Simulator for PDE-Electrical Analogy. - Yogesh Dilip Save; H. Narayanan; Sachin B. Patkar (VLSI Design, 2012)

Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields. - Prateek Saxena; Vinay B. Y. Kumar; Dilawar Singh; H. Narayanan; Sachin B. Patkar (PECCS, 2013)

Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. - Yogesh Dilip Save; H. Narayanan; Sachin B. Patkar (VLSI Design, 2013)

Solution of PDEs-electrically coupled systems with electrical analogy. - Yogesh Dilip Save; H. Narayanan; Sachin B. Patkar (Integr., 2013)

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping. - Vinay B. Y. Kumar; Shovan Maity; Sachin B. Patkar (ICCD, 2014)

FPGA-based implementation of M4RM for matrix multiplication over GF(2). - Vivek Kumar; Vinay B. Y. Kumar; Sachin B. Patkar (VDAT, 2014)

Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems. - Janak Porwal; Sanket Diwale; Vinay B. Y. Kumar; Sachin B. Patkar (VLSI-DAT, 2014)

Parallel two step random walk algorithm to analyze VLSI power grid networks. - Satyabrata Dash; Vivek Bangera; Vinay B. Y. Kumar; Gaurav Trivedi; Sachin B. Patkar (VDAT, 2015)

Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video. - Pinalkumar Engineer; Rajbabu Velmurugan; Sachin B. Patkar (VLSID, 2015)

Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies. - Vinay B. Y. Kumar; Pinalkumar Engineer; Mandar Datar 001; Yatish Turakhia; Saurabh Agarwal; Sanket Diwale; Sachin B. Patkar (CoRR, 2015)

Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. - Vinay B. Y. Kumar; Kulshreshth Dhiman; Mandar Datar 001; Akash Pacharne; H. Narayanan; Sachin B. Patkar (VLSID, 2016)

Lightweight Forth Programmable NoCs. - Vinay B. Y. Kumar; Deval Shah; Mandar Datar 001; Sachin B. Patkar (VLSID, 2018)

Computational Issues in Construction of 4-D Projective Spaces with Perfect Access Patterns for Higher Primes. - Shreeniwas N. Sapre; Sachin B. Patkar; Supratim Biswas (PaCT, 2019)

Accelerated Stereo Vision Using Nvidia Jetson and Intel AVX. - Imran A. Syed; Mandar Datar 001; Sachin B. Patkar (CVIP (2), 2020)

Real time System Implementation for Stereo 3D Mapping and Visual Odometry. - Yashwant Temburu; Mandar Datar 001; Simranjeet Singh; Vaibhav Malviya; Sachin B. Patkar (IPAS, 2020)

FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation. - Yogesh Mahajan; Shashank Obla; Mini K. Namboothiripad; Mandar J. Datar; Niraj N. Sharma; Sachin B. Patkar (VLSID, 2020)

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. - Riya Jain; Niraj N. Sharma; Farhad Merchant; Sachin B. Patkar; Rainer Leupers (CoRR, 2020)

Single Storage Semi-Global Matching for Real Time Depth Processing. - Prathmesh Sawant; Yashwant Temburu; Mandar Datar 001; Imran Ahmed; Vinayak Shriniwas; Sachin B. Patkar (CoRR, 2020)

Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC). - Pinalkumar Engineer; Rajbabu Velmurugan; Sachin B. Patkar (J. Real Time Image Process., 2020)

PA-PUF: A Novel Priority Arbiter PUF. - Simranjeet Singh; Srinivasu Bodapati; Sachin B. Patkar; Rainer Leupers; Anupam Chattopadhyay; Farhad Merchant (VLSI-SoC, 2022)

Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. - Simranjeet Singh; Furqan Zahoor; Gokulnath Rajendran; Sachin B. Patkar; Anupam Chattopadhyay; Farhad Merchant (ASP-DAC, 2023)

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. - Omar Ghazal; Simranjeet Singh; Tousif Rahman; Shengqi Yu; Yujin Zheng; Domenico Balsamo; Sachin B. Patkar; Farhad Merchant; Fei Xia 001; Alex Yakovlev; Rishad A. Shafik (ISLPED, 2023)

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. - Simranjeet Singh; Elmira Moussavi; Christopher Bengel; Sachin B. Patkar; Rainer Waser; Rainer Leupers; Vikas Rana; Vivek Pachauri; Stephan Menzel; Farhad Merchant (NANOARCH, 2023)

Finite State Automata Design using 1T1R ReRAM Crossbar. - Simranjeet Singh; Omar Ghazal; Chandan Kumar Jha 001; Vikas Rana; Rolf Drechsler; Rishad A. Shafik; Alex Yakovlev; Sachin B. Patkar; Farhad Merchant (NEWCAS, 2023)

Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. - Simranjeet Singh; Furqan Zahoor; Gokulnath Rajendran; Vikas Rana; Sachin B. Patkar; Anupam Chattopadhyay; Farhad Merchant (NEWCAS, 2023)

CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. - Niraj N. Sharma; Riya Jain; Mohana Madhumita Pokkuluri; Sachin B. Patkar; Rainer Leupers; Rishiyur S. Nikhil; Farhad Merchant (J. Syst. Archit., 2023)

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. - Simranjeet Singh; Chandan Kumar Jha 001; Ankit Bende; Phrangboklang Lyngton Thangkhiew; Vikas Rana; Sachin B. Patkar; Rolf Drechsler; Farhad Merchant (IEEE Embed. Syst. Lett., 2023)

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. - Simranjeet Singh; Chandan Kumar Jha 001; Ankit Bende; Vikas Rana; Sachin B. Patkar; Rolf Drechsler; Farhad Merchant (ASPDAC, 2024)

Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow. - Dhruva S. Hegde; Mandar Datar 001; Manish Prajapati; Sachin B. Patkar; Gaurav Trivedi (VDAT, 2024)

In-Memory Mirroring: Cloning Without Reading. - Simranjeet Singh; Ankit Bende; Chandan Kumar Jha 001; Vikas Rana; Rolf Drechsler; Sachin B. Patkar; Farhad Merchant (VLSI-SoC, 2024)

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. - Ankit Bende; Simranjeet Singh; Chandan Kumar Jha 001; Tim Kempen; Felix Cüppers; Christopher Bengel; Andre Zambanini; Dennis Nielinger; Sachin B. Patkar; Rolf Drechsler; Rainer Waser; Farhad Merchant; et al. (VLSID, 2024)

Python-based DSL for generating Verilog model of Synchronous Digital Circuits. - Mandar Datar 001; Dhruva S. Hegde; Vendra Durga Prasad; Manish Prajapati; Neralla Manikanta; Devansh Gupta; Janampalli Pavanija; Pratyush Pare; Akash; Shivam Gupta; Sachin B. Patkar (CoRR, 2024)

Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms. - Simranjeet Singh; Farhad Merchant; Sachin B. Patkar (CoRR, 2024)