Area-efficient and fast sign detection for four-moduli set RNS {2n -1, 2n, 2n +1, 22n +1}. - Chip-Hong Chang; Sachin Kumar 006 (ISCAS, 2014)

A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}. - Sachin Kumar 006; Chip-Hong Chang (ASICON, 2015)

A VLSI-efficient signed magnitude comparator for { 2n-1, 2n, 2n +2n+1-1} RNS. - Sachin Kumar 006; Chip-Hong Chang (ISCAS, 2016)

A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n-1, 2n, 2n+1}. - Sachin Kumar 006; Chip-Hong Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

New Algorithm for Signed Integer Comparison in {2n+k, 2n-1, 2n+1, 2n±1-1} and Its Efficient Hardware Implementation. - Sachin Kumar 006; Chip-Hong Chang; Thian Fatt Tay (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS 2n-1, 2n, 2n+ 1, 2n+1-1, 2n-1-1. - Sachin Kumar 006; Chip-Hong Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)