Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology. - Shankar Singh; Sachin Maheshwari; Poorn Chandra Pandey (Int. J. Manuf. Res., 2007)

Experimental results and analysis for Electrical Discharge Machining (EDM) of aluminium metal matrix composites with powder-mixed dielectric: Lenth's method. - Shankar Singh; Sachin Maheshwari; Aloke Dey; Poorn Chandra Pandey (Int. J. Manuf. Technol. Manag., 2010)

Neural-Network- Based Modeling of Electric Discharge Machining Process. - Pushpendrai Singh Bharti; Sachin Maheshwari; Chitra Sharma (SOCO, 2011)

Characterization of Logical Effort for Improved Delay. - Sachin Maheshwari; Himadri Singh Raghav; Anu Gupta (VDAT, 2013)

Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology. - Sachin Maheshwari; Rameez Raza; Pramod Kumar; Anu Gupta (VDAT, 2013)

Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology. - Himadri Singh Raghav; Sachin Maheshwari; B. Prasad Singh (VDAT, 2013)

Logical effort based power-delay-product optimization. - Sachin Maheshwari; Jimit Patel; Sumit K. Nirmalkar; Anu Gupta (ICACCI, 2014)

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (ECCTD, 2017)

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (PATMOS, 2018)

Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (Integr., 2018)

Adiabatic Implementation of Manchester Encoding for Passive NFC System. - Sachin Maheshwari; Izzet Kale (DATE, 2019)

Impact of Adiabatic Logic Families on the Power-Clock Generator Energy Efficiency. - Sachin Maheshwari; Izzet Kale (PRIME, 2019)

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (Integr., 2019)

Analysing and Measuring the Performance ofMemristive Integrating Amplifiers. - Jiaqi Wang 001; Alexander Serb; Christos Papavassiliou; Sachin Maheshwari; Themistoklis Prodromakis (CoRR, 2020)

Hybrid CMOS/Memristor Circuit Design Methodology. - Sachin Maheshwari; Spyros Stathopoulos; Jiaqi Wang 001; Alexander Serb; Yihan Pan; Lieuwe B. Leene; Christos Papavassiliou; Timothy G. Constandinou; Themistoklis Prodromakis (CoRR, 2020)

Optimal design of flux for submerged arc weld properties based on RSM coupled with GRA and PCA. - Brijpal Singh; Zahid A. Khan; Arshad Noor Siddiquee; Sachin Maheshwari (Int. J. Manuf. Technol. Manag., 2020)

An Adiabatic Regenerative Capacitive Artificial Neuron. - Sachin Maheshwari; Alexander Serb; Christos Papavassiliou; Themistoklis Prodromakis (ISCAS, 2021)

Analysing and measuring the performance of memristive integrating amplifiers. - Jiaqi Wang 001; Alexantrou Serb; Christos Papavassiliou; Sachin Maheshwari; Themis Prodromakis (Int. J. Circuit Theory Appl., 2021)

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits. - Sachin Maheshwari; Viv A. Bartlett; Izzet Kale (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps. - Sachin Maheshwari; Spyros Stathopoulos; Jiaqi Wang 001; Alexander Serb; Yihan Pan; Andrea Mifsud; Lieuwe B. Leene; Jiawei Shen; Christos Papavassiliou; Timothy G. Constandinou; Themistoklis Prodromakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout. - Sachin Maheshwari; Spyros Stathopoulos; Jiaqi Wang 001; Alexander Serb; Yihan Pan; Andrea Mifsud; Lieuwe B. Leene; Jiawei Shen; Christos Papavassiliou; Timothy G. Constandinou; Themistoklis Prodromakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A CMOS-based Characterisation Platform for Emerging RRAM Technologies. - Andrea Mifsud; Jiawei Shen; Peilong Feng; Lijie Xie; Chaohan Wang; Yihan Pan; Sachin Maheshwari; Shady Agwa; Spyros Stathopoulos; Shiwei Wang 001; Alexander Serb; Christos Papavassiliou; et al. (ISCAS, 2022)

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing. - Sachin Maheshwari; Alexander Serb; Christos Papavassiliou; Themistoklis Prodromakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Memristor-based Tuneable Offset Comparator. - Sachin Maheshwari; Jiaqi Wang 001; Alexander Serb; Themistoklis Prodromakis (NEWCAS, 2023)

Low Offset, High-Resolution Threshold Logic Design in 22nm FDSOI. - Himadri Singh Raghav; Sachin Maheshwari; Mike Smart; Alexander Serb (ISCAS, 2025)

The Adiabatic Capacitive Neuron: A Cross CMOS Technology Performance Comparison. - Himadri Singh Raghav; Mike Smart; Sachin Maheshwari; Alexander Serb (ISCAS, 2025)