A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. - Vaibhav Verma; Sachin Taneja; Pritender Singh; Sanjeev Kumar Jain (SoCC, 2015)

A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. - Sachin Taneja; Anastacia B. Alvarez; Gopalakrishnan Sadagopan; Massimo Alioto (A-SSCC, 2017)

Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems. - Sachin Taneja; Massimo Alioto (CoRR, 2018)

Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. - Sachin Taneja; Anastacia B. Alvarez; Massimo Alioto (IEEE J. Solid State Circuits, 2018)

Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper). - Massimo Alioto; Sachin Taneja (CICC, 2019)

PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion. - Sachin Taneja; Massimo Alioto (ESSCIRC, 2019)

Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff. - Muhammad Naveed Aman; Sachin Taneja; Biplab Sikdar 001; Kee Chaing Chua; Massimo Alioto (IEEE Internet Things J., 2019)

Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm. - Sachin Taneja; Massimo Alioto (ISCAS, 2020)

SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. - Viveka Konandur Rajanna; Sachin Taneja; Massimo Alioto (ESSDERC, 2021)

36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. - Sachin Taneja; Viveka Konandur Rajanna; Massimo Alioto (ISSCC, 2021)

PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion. - Sachin Taneja; Massimo Alioto (IEEE J. Solid State Circuits, 2021)

Fully Synthesizable Unified True Random Number Generator and Cryptographic Core. - Sachin Taneja; Massimo Alioto (IEEE J. Solid State Circuits, 2021)

A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. - Raghavan Kumar; Vikram B. Suresh; Sachin Taneja; Mark A. Anders 001; Steven Hsu; Amit Agarwal 001; Vivek De; Sanu Mathew (VLSI Technology and Circuits, 2022)

In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. - Sachin Taneja; Viveka Konandur Rajanna; Massimo Alioto (IEEE J. Solid State Circuits, 2022)

A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. - Raghavan Kumar; Avinash Varna 001; Carlos Tokunaga; Sachin Taneja; Vivek De; Sanu Mathew (ISSCC, 2023)

ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. - Joydeep Basu; Sachin Taneja; Viveka Konandur Rajanna; Tianqi Wang 004; Massimo Alioto (VLSI Technology and Circuits, 2023)

Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. - Animesh Gupta; Sayan Kumar; Viveka Konandur Rajanna; Sachin Taneja; Massimo Alioto (VLSI Technology and Circuits, 2023)

218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. - Sachin Taneja; Vikram B. Suresh; Raghavan Kumar; Vivek De; Sanu Mathew (VLSI Technology and Circuits, 2023)

A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. - Raghavan Kumar; Vikram B. Suresh; Sachin Taneja; Mark A. Anders 001; Steven Hsu; Amit Agarwal 001; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2023)

UFC: A Unified Accelerator for Fully Homomorphic Encryption. - Minxuan Zhou; Yujin Nam; Xuan Wang; Youhak Lee; Chris Wilkerson; Raghavan Kumar; Sachin Taneja; Sanu Mathew; Rosario Cammarota; Tajana Rosing (MICRO, 2024)

A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS. - Raghavan Kumar; Sachin Taneja; Vivek De; Sanu Mathew (VLSI Technology and Circuits, 2024)

A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. - Raghavan Kumar; Avinash L. Varna; Carlos Tokunaga; Sachin Taneja; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2024)

A 2455μm2 1.7Gbps Side-Channel Attack-Resistant Masked HMAC-SHA256 Accelerator in Intel 4 CMOS. - Sachin Taneja; Vikram B. Suresh; Raghavan Kumar; Vivek De; Sanu Mathew (CICC, 2025)

A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS. - Raghavan Kumar; Sachin Taneja; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2025)