Economical display generation of a large character set. - Koji Nezu; Sachio Naito (AFIPS Fall Joint Computing Conference, 1969)

An application of cellular logic for high speed decoding of minimum-redundancy codes. - Kenji Ohmori; Sachio Naito; T. Nanya; Koji Nezu (AFIPS Fall Joint Computing Conference (1), 1972)

Polytonic fault-free combinational circuits for alternate-data-retry. - Sachio Naito; Osamu Fujinawa (Syst. Comput. Jpn., 1987)

A fault-tolerant parallel processor modeled by a linear cellular automaton. - Masahiro Tsunoyama; Sachio Naito (FTCS, 1988)

A Fault-Tolerant FFT Processor. - Masahiro Tsunoyama; Sachio Naito (FTCS, 1991)

A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. - Yukiya Miura; Sachio Naito; Kozo Kinoshita (ISCAS, 1994)

A fault-tolerant parallel processor modeled by a two-dimensional linear cellular automaton. - Masataka Kawanaka; Masahiro Tsunoyama; Sachio Naito (Syst. Comput. Jpn., 1994)

A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs. - Yukiya Miura; Sachio Naito (IEICE Trans. Inf. Syst., 1995)