Design for testability using register-transfer level partial scan selection. - Akira Motohara; Sadami Takeoka; Toshinori Hosokawa; Mitsuyasu Ohta; Yuji Takai; Michihiro Matsumoto; Michiaki Muraoka (ASP-DAC, 1995)

On validating data hold times for flip-flops in sequential circuits. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara; Atsushi Murakami; Sadami Takeoka; Mitsuyasu Ohta (ITC, 2000)

On effective criterion of path selection for delay testing. - Masayasu Fukunaga; Seiji Kajihara; Sadami Takeoka; Shinichi Yosimura (ASP-DAC, 2003)

On Estimation of Fault Efficiency for Path Delay Faults. - Masayasu Fukunaga; Seiji Kajihara; Sadami Takeoka (Asian Test Symposium, 2003)

Evaluation of Delay Testing Based on Path Selection. - Masayasu Fukunaga; Seiji Kajihara; Sadami Takeoka; Shinichi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis. - Masayasu Fukunaga; Seiji Kajihara; Sadami Takeoka (IEICE Trans. Inf. Syst., 2005)