A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. - Koichiro Ishibashi; Kunihiro Komiyaji; Sadayuki Morita; Toshiro Aoto; Shuji Ikeda; Kyoichiro Asayama; Atsuyosi Koike; Toshiaki Yamanaka; Naotaka Hashimoto; Haruhito Iida; Fumio Kojima; Koichi Motohashi; et al. (IEEE J. Solid State Circuits, 1994)

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. - Akira Kotabe; Kenichi Osada; Naoki Kitai; Mio Fujioka; Shiro Kamohara; Masahiro Moniwa; Sadayuki Morita; Yoshikazu Saitoh (IEEE J. Solid State Circuits, 2005)

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. - Masafumi Onouchi; Kazuo Otsuga; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa (A-SSCC, 2011)

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology. - Kazuki Fukuoka; Ryo Mori; A. Kato; Motoshige Igarashi; Koji Shibutani; T. Yamaki; Shinji Tanaka; Koji Nii; Sadayuki Morita; Takao Koike; Noriaki Sakamoto (CICC, 2012)

An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. - Kazuo Otsuga; Masafumi Onouchi; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa (SoCC, 2012)

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor. - Takao Nomura; Ryo Mori; Munehiro Ito; Koji Takayanagi; Toshihiko Ochiai; Kazuki Fukuoka; Kazuo Otsuga; Koji Nii; Sadayuki Morita; Tomoaki Hashimoto; Tsuyoshi Kida; Junichi Yamada; et al. (CICC, 2013)