Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation. - Noriaki Oda; Hironori Imura; Naoyoshi Kawahara; Masayoshi Tagami; Hiroyuki Kunishima; Shuji Sone; Sadayuki Ohnishi; Kenta Yamada; Yumi Kakuhara; Makoto Sekine; Yoshihiro Hayashi; Kazuyoshi Ueno (IEICE Trans. Electron., 2007)

Accurate Modeling Method for Cu Interconnect. - Kenta Yamada; Hiroshi Kitahara; Yoshihiko Asai; Hideo Sakamoto; Norio Okada; Makoto Yasuda; Noriaki Oda; Michio Sakurai; Masayuki Hiroi; Toshiyuki Takewaki; Sadayuki Ohnishi; Manabu Iguchi 002; et al. (IEICE Trans. Electron., 2008)