Coding Last Level STT-RAM Cache for High Endurance and Low Power. - Sadegh Yazdanshenas; Marzieh Ranjbar Pirbasti; Mahdi Fazeli; Ahmad Patooghy (IEEE Comput. Archit. Lett., 2014)

Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. - Sadegh Yazdanshenas; Hossein Asadi 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. - Sadegh Yazdanshenas; Hossein Asadi 001; Behnam Khaleghi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs. - Kosuke Tatsumura; Sadegh Yazdanshenas; Vaughn Betz (FPT, 2016)

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. - Sadegh Yazdanshenas; Behnam Khaleghi; Paolo Ienne; Hossein Asadi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. - Sadegh Yazdanshenas; Kosuke Tatsumura; Vaughn Betz (FPGA, 2017)

Quantifying and mitigating the costs of FPGA virtualization. - Sadegh Yazdanshenas; Vaughn Betz (FPL, 2017)

Automatic circuit design and modelling for heterogeneous FPGAs. - Sadegh Yazdanshenas; Vaughn Betz (FPT, 2017)

Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs. - Andrew Boutros; Sadegh Yazdanshenas; Vaughn Betz (FPL, 2018)

Improving Confidentiality in Virtualized FPGAs. - Sadegh Yazdanshenas; Vaughn Betz (FPT, 2018)

Interconnect Solutions for Virtualized Field-Programmable Gate Arrays. - Sadegh Yazdanshenas; Vaughn Betz (IEEE Access, 2018)

You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference. - Andrew Boutros; Sadegh Yazdanshenas; Vaughn Betz (ACM Trans. Reconfigurable Technol. Syst., 2018)

Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. - Kosuke Tatsumura; Sadegh Yazdanshenas; Vaughn Betz (ACM Trans. Reconfigurable Technol. Syst., 2018)

Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. - Andrew Boutros; Mohamed Eldafrawy; Sadegh Yazdanshenas; Vaughn Betz (FPGA, 2019)

COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures. - Sadegh Yazdanshenas; Vaughn Betz (ACM Trans. Reconfigurable Technol. Syst., 2019)

The Costs of Confidentiality in Virtualized FPGAs. - Sadegh Yazdanshenas; Vaughn Betz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

FPGA Logic Block Architectures for Efficient Deep Learning Inference. - Mohamed Eldafrawy; Andrew Boutros; Sadegh Yazdanshenas; Vaughn Betz (ACM Trans. Reconfigurable Technol. Syst., 2020)