TuneLogic: Post-silicon tuning of dual-Vdd designs. - Stephen Bijansky; Sae Kyu Lee; Adnan Aziz (ISQED, 2009)

Evaluation of voltage stacking for near-threshold multicore computing. - Sae Kyu Lee; David M. Brooks; Gu-Yeon Wei (ISLPED, 2012)

Characterizing and evaluating voltage noise in multi-core near-threshold processors. - Xuan Zhang 001; Tao Tong; Svilen Kanev; Sae Kyu Lee; Gu-Yeon Wei; David M. Brooks (ISLPED, 2013)

A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter. - Sae Kyu Lee; Tao Tong; Xuan Zhang 001; David M. Brooks; Gu-Yeon Wei (VLSIC, 2015)

A multi-chip system optimized for insect-scale flapping-wing robots. - Xuan Zhang 001; Mario Lok; Tao Tong; Simon Chaput; Sae Kyu Lee; Brandon Reagen; Hyunkwang Lee; David M. Brooks; Gu-Yeon Wei (VLSIC, 2015)

Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators. - Brandon Reagen; Paul N. Whatmough; Robert Adolf; Saketh Rama; Hyunkwang Lee; Sae Kyu Lee; José Miguel Hernández-Lobato; Gu-Yeon Wei; David M. Brooks (ISCA, 2016)

A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications. - Tao Tong; Sae Kyu Lee; Xuan Zhang 001; David M. Brooks; Gu-Yeon Wei (IEEE J. Solid State Circuits, 2016)

Sub-uJ deep neural networks for embedded applications. - Paul N. Whatmough; Sae Kyu Lee; Gu-Yeon Wei; David M. Brooks (ACSSC, 2017)

14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications. - Paul N. Whatmough; Sae Kyu Lee; Hyunkwang Lee; Saketh Rama; David M. Brooks; Gu-Yeon Wei (ISSCC, 2017)

A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle. - Xuan Zhang 001; Mario Lok; Tao Tong; Sae Kyu Lee; Brandon Reagen; Simon Chaput; Pierre-Emile J. Duhamel; Robert J. Wood; David M. Brooks; Gu-Yeon Wei (IEEE J. Solid State Circuits, 2017)

A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter. - Sae Kyu Lee; Tao Tong; Xuan Zhang 001; David M. Brooks; Gu-Yeon Wei (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Ares: a framework for quantifying the resilience of deep neural networks. - Brandon Reagen; Udit Gupta; Lillian Pentecost; Paul N. Whatmough; Sae Kyu Lee; Niamh Mulholland; David M. Brooks; Gu-Yeon Wei (DAC, 2018)

A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET. - Sae Kyu Lee; Paul N. Whatmough; Niamh Mulholland; Patrick Hansen; David Brooks 001; Gu-Yeon Wei (ESSCIRC, 2018)

DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications. - Paul N. Whatmough; Sae Kyu Lee; David M. Brooks; Gu-Yeon Wei (IEEE J. Solid State Circuits, 2018)

A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators. - Paul N. Whatmough; Sae Kyu Lee; Marco Donato; Hsea-Ching Hsueh; Sam Likun Xi; Udit Gupta; Lillian Pentecost; Glenn G. Ko; David M. Brooks; Gu-Yeon Wei (VLSI Circuits, 2019)

A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs. - Sae Kyu Lee; Paul N. Whatmough; David Brooks 001; Gu-Yeon Wei (IEEE J. Solid State Circuits, 2019)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development. - Paul N. Whatmough; Marco Donato; Glenn G. Ko; Sae Kyu Lee; David Brooks 001; Gu-Yeon Wei (IEEE Micro, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators. - Sae Kyu Lee; Paul N. Whatmough; Marco Donato; Glenn G. Ko; David Brooks 001; Gu-Yeon Wei (IEEE J. Solid State Circuits, 2022)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)