A memory mapping approach based on network customization to design conflict-free parallel hardware architectures. - Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy (ACM Great Lakes Symposium on VLSI, 2014)

Conception d'architectures d'entrelaceurs parallèles pour les décodeurs de Turbo-Codes et de LDPC. (Designing Optimized Parallel Interleaver Architectures For Turbo And Ldpc Decoders). - Saeed Ur Reehman (2014)

In-place memory mapping approach for optimized parallel hardware interleaver architectures. - Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy; Awais Sani (DATE, 2015)