Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis. - Mohammad M. Ghahramani; Saeid Daneshgar; Michael Peter Kennedy; Oscar De Feo (ECCTD, 2007)

Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis. - Saeid Daneshgar; Michael Peter Kennedy (ICECS, 2008)

A qualitative analysis of a complementary differential LC injection-locked frequency divider based on direct injection. - Saeid Daneshgar; Michael Peter Kennedy (ISCAS, 2010)

Estimating the locking range of analog dividers through a phase-domain macromodel. - Paolo Maffezzoni; Dario D'Amore; Saeid Daneshgar; Michael Peter Kennedy (ISCAS, 2010)

Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part I: Qualitative Analysis. - Saeid Daneshgar; Oscar De Feo; Michael Peter Kennedy (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel. - Paolo Maffezzoni; Dario D'Amore; Saeid Daneshgar; Michael Peter Kennedy (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part II: Design Methodology. - Saeid Daneshgar; Oscar De Feo; Michael Peter Kennedy (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers. - Saeid Daneshgar; Zach Griffith; Munkyo Seo; Mark J. W. Rodwell (IEEE J. Solid State Circuits, 2014)

Millimeter-Wave Series Power Combining Using Sub-Quarter-Wavelength Baluns. - Hyun-Chul Park; Saeid Daneshgar; Zach Griffith; Miguel Urteaga; Byung-Sung Kim; Mark J. W. Rodwell (IEEE J. Solid State Circuits, 2014)

A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process. - Kristian N. Madsen; Timothy D. Gathman; Saeid Daneshgar; Thomas C. Oh; James Chingwei Li; James F. Buckwalter (IEEE J. Solid State Circuits, 2015)

A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS. - Kaushik Dasgupta; Saeid Daneshgar; Chintan Thakkar; Kunal Datta; James E. Jaussi; Bryan Casper (ESSCIRC, 2017)

A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO. - Saeid Daneshgar; Kaushik Dasgupta; Chintan Thakkar; Anandaroop Chakrabarti; Shuhei Yamada; Debabani Choudhury; James E. Jaussi; Bryan Casper (ISSCC, 2018)

A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO. - Shinwon Kang; Chintan Thakkar; Nathan Narevsky; Kaushik Dasgupta; Saeid Daneshgar; James E. Jaussi; Bryan Casper (ISSCC, 2018)

A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS. - Kaushik Dasgupta; Saeid Daneshgar; Chintan Thakkar; Shinwon Kang; Anandaroop Chakrabarti; Shuhei Yamada; Nathan Narevsky; Debabani Choudhury; James E. Jaussi; Bryan Casper (IEEE J. Solid State Circuits, 2018)

A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS. - Saeid Daneshgar; Hao Li 047; Taehwan Kim; Ganesh Balamurugan (IEEE J. Solid State Circuits, 2022)