Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design. - Saeroonter Oh; Jeongha Park; S. Simon Wong; H.-S. Philip Wong (ISQED, 2010)

Impact of III-V and Ge Devices on Circuit Performance. - Jeongha Park; Saeroonter Oh; Soyoung Kim; H.-S. Philip Wong; S. Simon Wong (IEEE Trans. Very Large Scale Integr. Syst., 2013)