Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. - Yves Blaquière; Yan Basile-Bellavance; Safa Berrima; Yvon Savaria (ISCAS, 2014)

A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. - Safa Berrima; Yves Blaquière; Yvon Savaria (ISCAS, 2017)

Sub-ps resolution programmable delays implemented in a Xilinx FPGA. - Safa Berrima; Yves Blaquière; Yvon Savaria (MWSCAS, 2017)

Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. - Safa Berrima; Yves Blaquière; Yvon Savaria (Integr., 2018)

Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. - Safa Berrima; Yves Blaquière; Yvon Savaria (IET Circuits Devices Syst., 2020)

Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. - Safa Berrima; Yves Blaquière; Yvon Savaria (IEEE Trans. Instrum. Meas., 2021)