Clock gating architectures for FPGA power reduction. - Safeen Huda; Muntasir Mallick; Jason Helge Anderson (FPL, 2009)

Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. - David Halupka; Safeen Huda; William Song; Ali Sheikholeslami; Koji Tsunoda; Chikako Yoshida; Masaki Aoki (ISSCC, 2010)

Charge recycling for power reduction in FPGA interconnect. - Safeen Huda; Jason Helge Anderson; Hirotaka Tamura (FPL, 2013)

A Novel STT-MRAM Cell With Disturbance-Free Read Operation. - Safeen Huda; Ali Sheikholeslami (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

On Hard Adders and Carry Chains in FPGAs. - Jason Luu; Conor McCullough; Sen Wang; Safeen Huda; Bo Yan; Charles Chiasson; Kenneth B. Kent; Jason Helge Anderson; Jonathan Rose; Vaughn Betz (FCCM, 2014)

Optimizing effective interconnect capacitance for FPGA power reduction. - Safeen Huda; Jason Helge Anderson; Hirotaka Tamura (FPGA, 2014)

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions. - Aynaz Vatankhahghadim; Safeen Huda; Ali Sheikholeslami (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Towards PVT-Tolerant Glitch-Free Operation in FPGAs. - Safeen Huda; Jason Helge Anderson (FPGA, 2016)

Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. - Safeen Huda; Jason Helge Anderson (ISPD, 2016)

Hybrid LUT/Multiplexer FPGA Logic Architectures. - S. Alexander Chin; Jason Luu; Safeen Huda; Jason Helge Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. - Safeen Huda; Jason Helge Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Optimizing FPGA Logic Block Architectures for Arithmetic. - Kevin E. Murray; Jason Luu; Matthew J. P. Walker; Conor McCullough; Sen Wang; Safeen Huda; Bo Yan; Charles Chiasson; Kenneth B. Kent; Jason Helge Anderson; Jonathan Rose; Vaughn Betz (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Full-stack Accelerator Search Technique for Vision Applications. - Dan Zhang 004; Safeen Huda; Ebrahim M. Songhori; Quoc V. Le; Anna Goldie; Azalia Mirhoseini (CoRR, 2021)

A full-stack search technique for domain optimized deep learning accelerators. - Dan Zhang 004; Safeen Huda; Ebrahim M. Songhori; Kartik Prabhu; Quoc V. Le; Anna Goldie; Azalia Mirhoseini (ASPLOS, 2022)

Learning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers. - Paras Jain 001; Safeen Huda; Martin Maas 001; Joseph E. Gonzalez; Ion Stoica; Azalia Mirhoseini (DATE, 2022)

ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. - Yash Akhauri; Ahmed F. AbouElhamayed; Jordan Dotzel; Zhiru Zhang; Alexander M. Rush; Safeen Huda; Mohamed S. Abdelfattah (EMNLP, 2024)

Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer. - Yazhou Zu; Alireza Ghaffarkhah; Hoang-Vu Dang; Brian Towles; Steven Hand 001; Safeen Huda; Adekunle Bello; Alexander Kolbasov; Arash Rezaei; Dayou Du; Steve Lacy; Hang Wang; et al. (NSDI, 2024)

Attamba: Attending To Multi-Token States. - Yash Akhauri; Safeen Huda; Mohamed S. Abdelfattah (CoRR, 2024)

HALO: Hardware-aware quantization with low critical-path-delay weights for LLM acceleration. - Rohan Juneja; Shivam Aggarwal; Safeen Huda; Tulika Mitra; Li-Shiuan Peh (CoRR, 2025)