Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. - Subhramita Basak; Dipankar Saha; Sagar Mukherjee; Sayan Chatterjee; Chandan Kumar Sarkar (ISED, 2012)

A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications. - Sagar Mukherjee; Dipankar Saha; Posiba Mostafa; Sayan Chatterjee; Chandan Kumar Sarkar (ISED, 2012)

Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit. - Dipankar Saha; Subhramita Basak; Sagar Mukherjee; Sayan Chatterjee; Chandan Kumar Sarkar (CoRR, 2013)

A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. - Dipankar Saha; Subhramita Basak; Sagar Mukherjee; Chandan Kumar Sarkar (CoRR, 2013)

Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET. - Sagar Mukherjee; Arka Dutta; Swarnil Roy; Kalyan Koley; Chandan Kumar Sarkar (Microelectron. J., 2015)

Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor. - Sagar Mukherjee; Kalyan Koley; Arka Dutta; Chandan Kumar Sarkar (IET Circuits Devices Syst., 2016)

Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance. - Sagar Mukherjee; Swarnil Roy; Arka Dutta; Chandan Kumar Sarkar (IET Circuits Devices Syst., 2016)

Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET. - Sagar Mukherjee; Arka Dutta; Swarnil Roy; Chandan Kumar Sarkar (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application. - Swarnil Roy; Sagar Mukherjee; Arka Dutta; Chandan Kumar Sarkar; Chayanika Bose (IET Circuits Devices Syst., 2019)