Statistics on concurrent fault and design error simulation. - Brian Grayson; Saghir A. Shaikh; Stephen A. Szygenda (ICCD, 1995)

CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator. - Saghir A. Shaikh; Silvian Goldenberg; Stephen A. Szygenda (PDPTA, 1996)

Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. - Youngmin Hur; Saghir A. Shaikh; Silvian Goldenberg; Dominik Kacprzak; Stephen A. Szygenda (Annual Simulation Symposium, 1997)

Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. - Saghir A. Shaikh; Stephen A. Szygenda (Annual Simulation Symposium, 1997)

Design of an experience-based assembly sequence planner for mechanical assemblies. - Arun Swaminathan; Saghir A. Shaikh; K. Suzanne Barber (Robotica, 1998)

Wire planning for performance and yield enhancement. - Charles Ouyang; Kyungsuk Ryu; Hans T. Heineken; Jitu Khare; Saghir A. Shaikh; Manuel d'Abreu (CICC, 2000)

Maximizing Wafer Productivity Through Layout Optimization. - Charles H. Ouyang; Hans T. Heineken; Jitendra Khare; Saghir A. Shaikh; Manuel d'Abreu (VLSI Design, 2000)

Manufacturability and Testability Oriented Synthesis. - Saghir A. Shaikh; Jitendra Khare; Hans T. Heineken (VLSI Design, 2000)

Test and Debug of Networking SoCs: A Case Study. - A. Bommireddy; Jitendra Khare; Saghir A. Shaikh; S.-T. Su (VTS, 2000)

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. - John T. Chen; Jitendra Khare; Ken Walker; Saghir A. Shaikh; Janusz Rajski; Wojciech Maly (ITC, 2001)

IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver. - Saghir A. Shaikh (ITC, 2004)

Practices in Testing of Mixed-Signal and RF SoCs. - Salem Abdennadher; Saghir A. Shaikh (Asian Test Symposium, 2005)

Challenges in High Speed Interface Testing. - Salem Abdennadher; Saghir A. Shaikh (Asian Test Symposium, 2005)

Practices in Mixed-Signal and RF IC Testing. - Salem Abdennadher; Saghir A. Shaikh (IEEE Des. Test Comput., 2007)

Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os. - Saghir A. Shaikh (VTS, 2013)

Fast BIST of I/O Pin AC specifications and inter-chip delays. - Stephen Sunter; Saghir A. Shaikh; Qing Lin (ITC, 2014)

Practices in High-Speed IO testing. - Salem Abdennadher; Saghir A. Shaikh (ETS, 2016)

Innovation Practices Track: Frontiers in Diagnosis and Debug. - Suriyaprakash Natarajan; Saghir A. Shaikh; Wu-Tung Cheng; Sankaran Menon (VTS, 2025)