Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. - Vinamra Benara; Sahithi Rampalli; Ziaul Choudhury; Suresh Purini; Uday Bondhugula (CoRR, 2018)

Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS. - Sahithi Rampalli; Natasha Sehgal; Ishita Bindlish; Tanya Tyagi; Pawan Kumar 001 (FPGA, 2019)

PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks. - Nagadastagiri Challapalle; Sahithi Rampalli; Makesh Chandran; Gurpreet S. Kalsi; Sreenivas Subramoney; John Sampson; Vijaykrishnan Narayanan (DATE, 2020)

GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures. - Nagadastagiri Challapalle; Sahithi Rampalli; Linghao Song; Nandhini Chandramoorthy; Karthik Swaminathan; John Sampson; Yiran Chen 001; Vijaykrishnan Narayanan (ISCA, 2020)

X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization. - Nagadastagiri Challapalle; Makesh Chandran; Sahithi Rampalli; Vijaykrishnan Narayanan (ISVLSI, 2020)

FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks. - Nagadastagiri Challapalle; Sahithi Rampalli; Nicholas Jao; Akshay Krishna Ramanathan; John Sampson; Vijaykrishnan Narayanan (J. Signal Process. Syst., 2020)