TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. - Sahu Sai Vikram; Vibha Panty; Mihir Mody; Madhura Purnaprajna (VLSID, 2018)

TileNET: Hardware accelerator for ternary Convolutional Neural Networks. - Sagar Eetha; Sruthi P. K.; Vibha Panty; Sahu Sai Vikram; Mihir Mody; Madhura Purnaprajna (Microprocess. Microsystems, 2021)