ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. - Sai Kiran Cherupally; Gaurav Srivastava 001; Shihui Yin; Deepak Kadetotad; Chisung Bae; Sang Joon Kim; Jae-sun Seo (ISCAS, 2019)

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation. - Sai Kiran Cherupally; Shihui Yin; Deepak Kadetotad; Chisung Bae; Sang Joon Kim; Jae-sun Seo (IEEE J. Solid State Circuits, 2020)

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression. - Sai Kiran Cherupally; Shihui Yin; Deepak Kadetotad; Gaurav Srivastava 001; Chisung Bae; Sang Joon Kim; Jae-sun Seo (IEEE Trans. Biomed. Circuits Syst., 2020)

Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. - Sai Kiran Cherupally; Adnan Siraj Rakin; Shihui Yin; Mingoo Seok; Deliang Fan; Jae-sun Seo (DAC, 2021)

Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. - Jyotishman Saikia; Shihui Yin; Sai Kiran Cherupally; Bo Zhang 105; Jian Meng; Mingoo Seok; Jae-Sun Seo (DATE, 2021)

A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. - Amitesh Sridharan; Shaahin Angizi; Sai Kiran Cherupally; Fan Zhang 069; Jae-Sun Seo; Deliang Fan (ESSCIRC, 2022)

A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-sun Seo (ESSCIRC, 2022)

Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection. - Sai Kiran Cherupally; Jian Meng; Adnan Siraj Rakin; Shihui Yin; Mingoo Seok; Deliang Fan; Jae-Sun Seo (IEEE Des. Test, 2022)

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-Sun Seo (IEEE J. Solid State Circuits, 2023)