Sai Lalith Chaitanya Ambatipudi

According to our database, Sai Lalith Chaitanya Ambatipudi authored at least 6 papers between 2018 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.

Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang

IEEE J. Solid State Circuits, 2020

50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.

Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang

Proceedings of the European Conference on Optical Communications, 2020

2019

A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.

Mayank Raj, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.

Kevin Zheng, Yohan Frans, Sai Lalith Ambatipudi, Santiago Asuncion, Hari Teja Reddy, Ken Chang, Boris Murmann

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 112-GB/S PAM4 Transmitter in 16NM FinFET.

Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.

James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018