A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. - James Hudner; Declan Carey; Ronan Casey; Kay Hearne; Pedro Wilson de Abreu Farias Neto; Ilias Chlis; Marc Erett; Chi Fung Poon; Asma Laraba; Hongtao Zhang 002; Sai Lalith Chaitanya Ambatipudi; David Mahashin; et al. (VLSI Circuits, 2018)

A 112-GB/S PAM4 Transmitter in 16NM FinFET. - Kee Hian Tan; Ping-Chuan Chiang; Yipeng Wang 003; Haibing Zhao; Arianne Roldan; Hongyuan Zhao; Nakul Narang; Siok-Wei Lim; Declan Carey; Sai Lalith Chaitanya Ambatipudi; Parag Upadhyaya; Yohan Frans; et al. (VLSI Circuits, 2018)

An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS. - Kevin Zheng; Yohan Frans; Sai Lalith Ambatipudi; Santiago Asuncion; Hari Teja Reddy; Ken Chang; Boris Murmann (VLSI Circuits, 2018)

A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. - Mayank Raj; Yohan Frans; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (VLSI Circuits, 2019)

50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (ECOC, 2020)

Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (IEEE J. Solid State Circuits, 2020)