Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs. - Kyungwook Chang; Sai Pentapati; Da Eun Shim; Sung Kyu Lim (ISLPED, 2018)

Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary. - Sai Surya Kiran Pentapati; Da Eun Shim; Sung Kyu Lim (ACM Great Lakes Symposium on VLSI, 2019)

Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs. - Da Eun Shim; Sai Pentapati; Jeehyun Lee 002; Yun Seop Yu; Sung Kyu Lim (ISLPED, 2019)

A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology. - Sai Pentapati; Lingjun Zhu; Lennart Bamberg; Da Eun Shim; Alberto García Ortiz; Sung Kyu Lim (IEEE Micro, 2019)

TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. - Yi-Chen Lu; Sai Surya Kiran Pentapati; Lingjun Zhu; Kambiz Samadi; Sung Kyu Lim (DAC, 2020)

Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. - Lennart Bamberg; Alberto García Ortiz; Lingjun Zhu; Sai Pentapati; Da Eun Shim; Sung Kyu Lim (DATE, 2020)

A Fast Learning-Driven Signoff Power Optimization Framework. - Yi-Chen Lu; Siddhartha Nath; Sai Surya Kiran Pentapati; Sung Kyu Lim (ICCAD, 2020)

Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs. - Sai Surya Kiran Pentapati; Kyungwook Chang; Vassilios Gerousis; Rwik Sengupta; Sung Kyu Lim (ICCAD, 2020)

Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs. - Sai Surya Kiran Pentapati; Sung Kyu Lim (DAC, 2021)

The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks. - Yi-Chen Lu; Sai Pentapati; Sung Kyu Lim (ISPD, 2021)

ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization. - Sai Surya Kiran Pentapati; Bon Woong Ku; Sung Kyu Lim (ISPD, 2021)

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs. - Pruek Vanna-Iampikul; Chengjia Shao; Yi-Chen Lu; Sai Pentapati; Sung Kyu Lim (ISPD, 2021)

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. - Lingjun Zhu; Lennart Bamberg; Sai Surya Kiran Pentapati; Kyungwook Chang; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Brian Cline; Saurabh Sinha; Xiaoqing Xu; Alberto García-Ortiz; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs. - Sai Pentapati; Sung Kyu Lim (ISPD, 2022)

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs. - Yi-Chen Lu; Sai Pentapati; Lingjun Zhu; Gauthaman Murali; Kambiz Samadi; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs. - Sai Pentapati; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2022)

On Legalization of Die Bonding Bumps and Pads for 3D ICs. - Sai Pentapati; Anthony Agnesina; Moritz Brunion; Yen-Hsiang Huang; Sung Kyu Lim (ISPD, 2023)

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs. - Pruek Vanna-Iampikul; Chengjia Shao; Yi-Chen Lu; Sai Pentapati; Yun Heo; Jae-Seung Choi; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation. - Yi-Chen Lu; Siddhartha Nath; Sai Pentapati; Sung Kyu Lim (ACM Trans. Design Autom. Electr. Syst., 2023)

Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs. - Sai Pentapati; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs. - Sai Pentapati; Kyungwook Chang; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

On Legalization of Die Bonding Bumps and Pads for 3-D ICs. - Yen-Hsiang Huang; Sai Pentapati; Anthony Agnesina; Moritz Brunion; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)