Sai Phaneendra P.

According to our database, Sai Phaneendra P. authored at least 15 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Optimization of Reversible Circuits Using Gate Pair Classification.

P. Sai Phaneendra, Chetan Vudadha, M. B. Srinivas

SN Comput. Sci., 2022

2018

Energy efficient design of CNFET-based multi-digit ternary adders.

Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas

Microelectron. J., 2018

2017

An ESOP Based Cube Decomposition Technique for Reversible Circuits.

Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas

Proceedings of the Reversible Computation - 9th International Conference, 2017

Optimizing the Reversible Circuits Using Complementary Control Line Transformation.

Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas

Proceedings of the Reversible Computation - 9th International Conference, 2017

2016

An Efficient Design Methodology for CNFET Based Ternary Logic Circuits.

Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2014

An Optimized Design of Reversible Quantum Comparator.

P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A New Design of an N-Bit Reversible Arithmetic Logic Unit.

Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2012

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.

Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.

Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.

Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

CNFET based ternary magnitude comparator.

Chetan Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas

Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011

A Prefix Based Reconfigurable Adder.

Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.

Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the International Symposium on Electronic System Design, 2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.

P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Unified Architecture for BCD and Binary Adder/Subtractor.

Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011