Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. - Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ICASSP (6), 2003)

Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (1), 2003)

A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2004)

Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. - Seng-Pan U.; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Instrum. Meas., 2004)

A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (2), 2005)

A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (2), 2005)

A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. - Jun-Xia Ma; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. - U. Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. - Li Ding; Sio Chan; Kim-Fai Wong; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. - He Gong Wei; U. Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ICECS, 2008)

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. - He Gong Wei; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2008)

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. - Sai-Weng Sin; U-Fat Chio; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. - Li Ding; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (APCCAS, 2010)

A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. - Yang Jiang 002; Kim-Fai Wong; Chen-Yan Cai; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2010)

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. - Sai-Weng Sin; Li Ding; Yan Zhu 001; He Gong Wei; Chi-Hang Chan; U. Fat Chio; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (ESSCIRC, 2010)

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. - Yang Jiang 002; Kim-Fai Wong; Chen-Yan Cai; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ICECS, 2010)

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. - Guohe Yin; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Zhihua Wang 001 (ICECS, 2010)

A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2010)

1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. - Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IET Circuits Devices Syst., 2010)

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2010)

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. - U-Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. - He Gong Wei; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (VLSI Design, 2010)

A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (A-SSCC, 2011)

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. - Chi-Hang Chan; Yan Zhu 001; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. - Si-Seng Wong; U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. - U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ESSCIRC, 2011)

Hybrid loopfilter sigma-delta modulator with NTF zero compensation. - Arshad Hussain; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISOCC, 2011)

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. - He Gong Wei; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (ISSCC, 2011)

A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. - Yun Du; Tao He; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. - Tao He; Yun Du; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. - Wen-Lan Wu; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. - Si-Seng Wong; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (CICC, 2012)

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. - Rui Wang; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Zhihua Wang 001; Rui Paulo Martins (ESSCIRC, 2012)

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. - Guohe Yin; He Gong Wei; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Zhihua Wang 001; Rui Paulo Martins (ESSCIRC, 2012)

A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. - Tao He; Yang Jiang 002; Yun Du; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2012)

An ELD tracking compensation technique for active-RC CT ΣΔ modulators. - Chen-Yan Cai; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (MWSCAS, 2012)

A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. - He Gong Wei; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. - Yun Du; Tao He; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2013)

A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. - Wen-Lan Wu; Yan Zhu 001; Li Ding; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2013)

A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. - Li Ding; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (MWSCAS, 2013)

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2013)

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. - Si-Seng Wong; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. - Da Feng; Franco Maloberti; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISCAS, 2014)

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2015)

26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISSCC, 2015)

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. - Yan Lu 002; Junmin Jiang; Wing-Hung Ki; C. Patrick Yue; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISSCC, 2015)

Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters. - Da Feng; Franco Maloberti; Sai-Weng Sin; Rui Paulo Martins (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. - Jianyu Zhong; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. - Yuan Ren; Sai-Weng Sin; Chi-Seng Lam; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2016)

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. - Dante Gabriel Muratore; Alper Akdikmen; Edoardo Bonizzoni; Franco Maloberti; U. Fat Chio; Sai-Weng Sin; Rui Paulo Martins (ESSCIRC, 2016)

A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2016)

A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. - Wei Li; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISIC, 2016)

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. - Mo Huang; Yan Lu 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. - Mo Huang; Yan Lu 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Wing-Hung Ki (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. - Jianwei Liu 005; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. - U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (A-SSCC, 2017)

CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. - Chi-Wa U; Chi-Seng Lam; Man-Kay Law; Sai-Weng Sin; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (IECON, 2017)

A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. - Xia Du; Chi-Seng Lam; Sai-Weng Sin; Man-Kay Law; Franco Maloberti; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (ISIE, 2017)

A sub-1V 78-nA bandgap reference with curvature compensation. - Ziyang Luo; Yan Lu 002; Mo Huang; Junmin Jiang; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (Microelectron. J., 2017)

Metastablility in SAR ADCs. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Boris Murmann; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. - Yan Lu 002; Haojuan Dai; Mo Huang; Man-Kay Law; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. - Liang Qi 002; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. - Arshad Hussain; Sai-Weng Sin; Chi-Hang Chan; Ben Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{ mathrm {cm}}$ -Based Switching. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Fan Ye 001; Junyan Ren; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Power Quality Indexes Measurement System Platform with Remote Alarm Notification. - Jianyang Deng; Chi-Seng Lam; Man-Chung Wong; Lei Wang 067; Sai-Weng Sin; Rui Paulo Martins (IECON, 2018)

Design and Control of An Integrated 3-Level Boost Converter under DCM Operation. - Yiwei Tan; Chi-Seng Lam; Sai-Weng Sin; Man-Chung Wong; Rui Paulo Martins (ISCAS, 2018)

A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (VLSI Circuits, 2018)

Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM. - Yu-Jun Mao; Chi-Seng Lam; Sai-Weng Sin; Man-Chung Wong; Rui Paulo Martins (J. Electr. Comput. Eng., 2018)

Quick and cost-efficient A/D converter static characterization using low-precision testing signal. - Wei Wei Qin; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (Microelectron. J., 2018)

A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches. - Da Feng; Edoardo Bonizzoni; Franco Maloberti; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current. - Jiaji Mao; Mingqiang Guo; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller. - Ya-Jie Wu; Chi-Seng Lam; Man-Chung Wong; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation. - Wen-Liang Zeng; Chi-Seng Lam; Sai-Weng Sin; Franco Maloberti; Man-Chung Wong; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. - Liang Qi 002; Sai-Weng Sin; Rui Paulo Martins (ASICON, 2019)

A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. - Junhao Liang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins; Hanjun Jiang (A-SSCC, 2019)

A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (A-SSCC, 2019)

A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (CICC, 2019)

A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (ISSCC, 2019)

A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (VLSI Circuits, 2019)

An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. - U-Fat Chio; Kuo-Chih Wen; Sai-Weng Sin; Chi-Seng Lam; Yan Lu 002; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 550- $ mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $ Sigma Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

Design of KY Converter With Constant On-Time Control Under DCM Operation. - Wen-Liang Zeng; Zi-Yang Lin; Chi-Seng Lam; Man-Kay Law; Sai-Weng Sin; Franco Maloberti; Man-Chung Wong; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. - Dongyang Jiang; Liang Qi 002; Sai-Weng Sin; Franco Maloberti; Rui Paulo Martins (VLSI Circuits, 2020)

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (IEEE Access, 2020)

Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation. - Wen-Ming Zheng; Wen-Liang Zeng; Chi-Wa U; Chi-Seng Lam; Yan Lu 002; Sai-Weng Sin; Man-Chung Wong; Rui Paulo Martins (J. Circuits Syst. Comput., 2020)

A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (IEEE J. Solid State Circuits, 2020)

Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging. - Ji-Xuan Li; Sai-Weng Sin; U. Fat Chio; Ya-Jie Wu; Chi-Seng Lam; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration. - Hanyu Wang; Sai-Weng Sin; Chi-Seng Lam; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery. - Wen-Liang Zeng; Edoardo Bonizzoni; Chi-Wa U; Chi-Seng Lam; Sai-Weng Sin; U. Fat Chio; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application. - Wen-Liang Zeng; Yuan Ren; Chi-Seng Lam; Sai-Weng Sin; Weng-Keong Che; Ran Ding; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

Advances in Continuous-time MASH ΔΣ Modulators. - Liang Qi 002; Xinyu Qin; Sai-Weng Sin; Chixiao Chen; Fan Ye 001; Guoyong Shi; Guoxing Wang (ASICON, 2021)

A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM. - Wen-Liang Zeng; Caolei Pan; Chi-Seng Lam; Sai-Weng Sin; Chenchang Zhan; Rui Paulo Martins (A-SSCC, 2021)

Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. - Xinyu Qin; Jingying Zhang; Liang Qi 002; Sai-Weng Sin; Rui Paulo Martins; Guoxing Wang (ISCAS, 2021)

Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs. - Mingqiang Guo; Sai-Weng Sin; Rui Paulo Martins (ISOCC, 2021)

Bird's-eye view of analog and mixed-signal chips for the 21st century. - Rui Paulo Martins; Pui-In Mak; Chi-Hang Chan; Jun Yin 001; Yan Zhu 001; Yong Chen 005; Yan Lu 002; Man-Kay Law; Sai-Weng Sin (Int. J. Circuit Theory Appl., 2021)

A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation. - Dongyang Jiang; Liang Qi 002; Sai-Weng Sin; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. - Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Gang Xiao 001; Rui Paulo Martins (CICC, 2022)

A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. - Ke Li; Sai-Weng Sin; Liang Qi 002; Weibing Zhao; Guoxing Wang; Rui Paulo Martins (ISCAS, 2022)

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. - Danfeng Zhai; Wenning Jiang; Xinru Jia; Jingchao Lan; Mingqiang Guo; Sai-Weng Sin; Fan Ye 001; Qi Liu 010; Junyan Ren; Chixiao Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. - Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Dengke Xu; Guoxing Wang; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. - Liang Qi 002; Yuekai Liu; Sai-Weng Sin; Xinpeng Xing; Guoxing Wang; Maurits Ortmanns; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters. - Ya-Jie Wu; Wai-Hei Choi; Chi-Seng Lam; Man-Chung Wong; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Weightings in Incremental ADCs: A Tutorial Review. - Ruiqi Gao; Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Biao Wang; Guoxing Wang; Rui Paulo Martins (CICC, 2023)

A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter. - Wen-Liang Zeng; Guigang Cai; Chon-Fai Lee; Chi-Seng Lam; Yan Lu 002; Sai-Weng Sin; Rui Paulo Martins (ISSCC, 2023)

IoT Cloud-Edge Reconfigurable Mixed-Signal Smart Meter Platform for Arc Fault Detection. - Ya-Jie Wu; Ricardo Brito; Wai-Hei Choi; Chi-Seng Lam; Man-Chung Wong; Sai-Weng Sin; Rui Paulo Martins (IEEE Internet Things J., 2023)

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. - Jingying Zhang; Sai-Weng Sin; Yan Liu 016; Fan Ye 001; Guoxing Wang; Maurits Ortmanns; Liang Qi 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. - Kaiquan Chen; Biao Wang; Yan Liu 016; Fan Ye 001; Sai-Weng Sin; Guoxing Wang; Yong Lian 001; Liang Qi 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. - Shulin Zhao 004; Mingqiang Guo; Liang Qi 002; Dengke Xu; Guoxing Wang; Rui Paulo Martins; Sai-Weng Sin (IEEE J. Solid State Circuits, 2023)

A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications. - Caolei Pan; Wen-Liang Zeng; Chi-Seng Lam; Sai-Weng Sin; Chenchang Zhan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2023)

A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. - Mingqiang Guo; Liang Qi 002; Weibing Zhao; Gang Xiao 001; Rui Paulo Martins; Sai-Weng Sin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator. - Yue Hu; Yuekai Liu; Xinyu Qin; Yan Liu 016; Mingqiang Guo; Sai-Weng Sin; Guoxing Wang; Yong Lian 001; Liang Qi 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. - Gaofeng Tan; Xinyu Qin; Yan Liu 016; Mingqiang Guo; Sai-Weng Sin; Guoxing Wang; Yong Lian 001; Liang Qi 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 5.76GS/s 180MHz-BW 74.1dB-DR 2x TI Extrapolated CT DSM with Broadband Hybrid-Inputs Current-Mode Adder in 28nm CMOS. - Yuekai Liu; Meng Guo; Yichen Jin; Yan Liu 016; Mingqiang Guo; Sai-Weng Sin; Zhichao Tan; Liang Qi 002 (A-SSCC, 2024)

A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter. - Haoyu Gong; Wen-Liang Zeng; Mingqiang Guo; Chi-Seng Lam; Shulin Zhao 004; Rui Paulo Martins; Sai-Weng Sin (CICC, 2024)

A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. - Ke Li; Xianyu Congzhou; Liang Qi 002; Mingqiang Guo; Rui Paulo Martins; Sai-Weng Sin (CICC, 2024)

A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS. - Xinyu Qin; Yichen Jin; Guoxing Wang; Sai-Weng Sin; Maurits Ortmanns; Yong Lian 001; Liang Qi 002 (CICC, 2024)

Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing. - Ran Zhang; Ka-Fai Un; Zhensheng Li; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (ICTA, 2024)

A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. - Ran Zhang; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Dengke Xu; Weibing Zhao; Rui Paulo Martins; Franco Maloberti; Sai-Weng Sin (ISCAS, 2024)

A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification. - Haoyu Li; Boyang Wang; Hongjiang Chen; Sai-Weng Sin; Yutao Peng; Xizhu Peng; He Tang; Chao Fan; Liang Qi 002; Rui Paulo Martins; Mingqiang Guo (CICC, 2025)

A 0.0022 mm2, 2 GS/s Resettable VCO-Based ADC With-out Quantization Noise Shaping. - Tao Lu; Zixiang Liu; Hao Yang; Sai-Weng Sin; Robert Bogdan Staszewski; Fujiang Lin; Liheng Lou; Yizhe Hu (CICC, 2025)

A 4-Phase Adaptive On-Time Controlled Buck Converter With Auto-Synchronized Dynamic Frequency and Transient-Enhancement Techniques. - Zhiming He; Sai-Weng Sin; Rui Paulo Martins; Yan Lu 002 (ISCAS, 2025)

A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering. - Ke Li; Haoyu Gong; Xianyu Congzhou; Zhensheng Li; Liang Qi 002; Mingqiang Guo; Rui Paulo Martins; Sai-Weng Sin (IEEE J. Solid State Circuits, 2025)

A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation. - Ran Zhang; Xueru Cen; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Dual-Inductor Quad-Path Hybrid Buck (2L4PHB) Converter With Reduced Inductor Current. - Wen-Liang Zeng; Guigang Cai; Yan Lu 002; Sai-Weng Sin; Rui Paulo Martins; Chi-Seng Lam (IEEE J. Solid State Circuits, 2025)