A CMOS High-Q LC Eight-Path Bandpass Filter for Wireless Broadband Applications. - Ahmed El Oualkadi; Jean-Marie Paillot; Said Belkouch; Denis Flandre (ICECS, 2007)

FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. - Michael Guarisco; Hassan Rabah; Yves Berviller; Serge Weber; Said Belkouch (SoCC, 2009)

Design optimization of the quantization and a pipelined 2D-DCT for real-time applications. - Anas Hatim; Said Belkouch; Mohamed El Aakif; Moha M'rabet Hassani; Noureddine Chabini (Multim. Tools Appl., 2013)

Fast enumeration-based modulo scheduling heuristic for VLIW architectures. - Mounir Bahtat; Said Belkouch; Philippe Elleaume; Phillipe Le Gall (ICM, 2014)

Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect. - Abdessamad Klilou; Said Belkouch; Philippe Elleaume; Philippe Le Gall; François Bourzeix; Moha M'rabet Hassani (EURASIP J. Adv. Signal Process., 2014)

Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders. - Noureddine Chabini; Said Belkouch (AICCSA, 2015)

Real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors. - Abdessamad Klilou; François Bourzeix; Omar Bourja; Yahya Zennayi; Lhoussein Mabrouk; Said Belkouch (ISDA, 2015)

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage. - Mounir Bahtat; Said Belkouch; Philippe Elleaume; Philippe Le Gall (EURASIP J. Adv. Signal Process., 2016)

Efficient architecture for direct 8 × 8 2D DCT computations with earlier zigzag ordering. - Anas Hatim; Said Belkouch; Abderrahim Benslimane; Moha M'rabet Hassani; Tayeb Sadiki (Multim. Tools Appl., 2016)

Novel parallel Givens QR decomposition implementation on VLIW architecture with Efficient memory access for real time image processing applications. - Mohamed Najoui; Anas Hatim; Said Belkouch (BDCA, 2017)

VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing. - Mohamed Najoui; Mounir Bahtat; Anas Hatim; Said Belkouch; Noureddine Chabini (J. Circuits Syst. Comput., 2017)

Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection. - Lhoussein Mabrouk; Sylvain Huet; Dominique Houzet; Said Belkouch; Abdelkrim Hamzaoui; Yahya Zennayi (ATSIP, 2018)

Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection. - Lhoussein Mabrouk; Dominique Houzet; Sylvain Huet; Said Belkouch; Abdelkrim Hamzaoui; Yahya Zennayi (CIST, 2018)

Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture. - Mohamed Najoui; Anas Hatim; Said Belkouch; Noureddine Chabini (J. Circuits Syst. Comput., 2020)

Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU-GPU platforms. - Lhoussein Mabrouk; Sylvain Huet; Dominique Houzet; Said Belkouch; Abdelkrim Hamzaoui; Yahya Zennayi (J. Real Time Image Process., 2020)

An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP. - Abdessamad Klilou; Assia Arsalane; Mohamed Najoui; Said Belkouch (Microprocess. Microsystems, 2021)

An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs. - Noureddine Chabini; Said Belkouch; Mohamed Najoui (ICECOCS, 2022)

Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. - Mohamed Najoui; Mounir Bahtat; Abdessamad Klilou; Anas Hatim; Said Belkouch; Atman Jbari; Noureddine Chabini (Comput. Electr. Eng., 2022)