A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices. - Saihua Lin; Rong Luo; Huazhong Yang; Hui Wang 004 (APCCAS, 2006)

Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS. - Saihua Lin; Hongli Gao; Huazhong Yang (PATMOS, 2006)

Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling. - Saihua Lin; Huazhong Yang (PATMOS, 2006)

A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme. - Saihua Lin; Huazhong Yang; Rong Luo (ISCAS, 2007)

High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit. - Saihua Lin; Huazhong Yang; Rong Luo (ISVLSI, 2007)

A Novel gamma d/n, RLCG Transmission Line Model Considering Complex RC(L) Loads. - Saihua Lin; Huazhong Yang; Rong Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application. - Saihua Lin; Yu Wang 002; Rong Luo; Huazhong Yang (ASP-DAC, 2008)

A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems. - Saihua Lin; Huazhong Yang; Rong Luo (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Pi Coil: A New Element for Bandwidth Extension. - Saihua Lin; Dawei Huang; Simon Wong (IEEE Trans. Circuits Syst. II Express Briefs, 2009)