Pipelined orthogonal digital lattice filters. - Sailesh K. Rao; Thomas Kailath (ICASSP, 1984)

Design of minimal-degree compensators with assignable poles or structure. - Sailesh K. Rao; Chi-Tsong Chen (Autom., 1987)

Array architectures for iterative algorithms. - Hosagrahar Visvesvaraya Jagadish; Sailesh K. Rao; Thomas Kailath (Proc. IEEE, 1987)

Regular iterative algorithms and their implementation on processor arrays. - Sailesh K. Rao; Thomas Kailath (Proc. IEEE, 1988)

The matrix transform chip. - Sailesh K. Rao (ICCD, 1989)

Communication reduction for distributed sparse matrix factorization on a processor mesh. - Ponnuswamy Sadayappan; Sailesh K. Rao (SC, 1989)

A design environment for high performance VLSI signal processing. - Sailesh K. Rao; Mehdi Hatamian; Bryan D. Ackland (ICCD, 1990)

On the Analysis of Synchronous Computing Systems. - Juan-Manuel Jover; Thomas Kailath; Hanoch Lev-Ari; Sailesh K. Rao (SIAM J. Comput., 1990)

The Rectilinear Steiner Arborescence Problem. - Sailesh K. Rao; P. Sadayappan; Frank K. Hwang; Peter W. Shor (Algorithmica, 1992)

A 200 MHz CMOS broad-band switching chip. - Jay H. O'Neill; Bryan D. Ackland; Sailesh K. Rao; Mehdi Hatamian (IEEE J. Solid State Circuits, 1993)

Application Specific Memories for ATM Packet Switching. - Alex G. Dickinson; Chris J. Nicol; Sailesh K. Rao; Mehdi Hatamian (ISCAS, 1994)

The ATM physical layer. - Sailesh K. Rao; Mehdi Hatamian (Comput. Commun. Rev., 1995)

100BASE-T2: 100 Mbit/s Ethernet over Two Pairs of Category-3 Cabling. - Giovanni Cherubini; John Creigh; Sedat Ölçer; Sailesh K. Rao; Gottfried Ungerboeck (ICC (2), 1997)

100BASE-T2: a new standard for 100 Mb/s Ethernet transmission over voice-grade cables. - Giovanni Cherubini; Sedat Ölçer; Gottfried Ungerboeck; John Creigh; Sailesh K. Rao (IEEE Commun. Mag., 1997)