Power reduction techniques for an 8-core xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (ESSCIRC, 2009)

Nahalem-EX CPU architecture. - Sailesh Kottapalli; Jeff Baxter (Hot Chips Symposium, 2009)

A 45nm 8-core enterprise Xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli (ISSCC, 2009)

Westmere-EX: A 20 thread server CPU. - Dheemanth Nagaraj; Sailesh Kottapalli (Hot Chips Symposium, 2010)

A 45 nm 8-Core Enterprise Xeon¯ Processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (IEEE J. Solid State Circuits, 2010)

Ivybridge server architecture: A converged server. - Irma Esmer Papazian; Sailesh Kottapalli (Hot Chips Symposium, 2014)

Ivy Bridge Server: A Converged Design. - Irma Esmer Papazian; Sailesh Kottapalli; Jeff Baxter; Jeff Chamberlain; Geetha Vedaraman; Brian Morris (IEEE Micro, 2015)

Cascade Lake: Next Generation Intel Xeon Scalable Processor. - Mohamed Arafa; Bahaa Fahim; Sailesh Kottapalli; Akhilesh Kumar; Lily Pao Looi; Sreenivas Mandava; Andy Rudoff; Ian M. Steiner; Bob Valentine; Geetha Vedaraman; Sujal Vora (IEEE Micro, 2019)