Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications. - Saiyu Ren; Ray Siferd; Robert Blumgold (SoCC, 2004)

Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS. - Saiyu Ren; Ray Siferd (SoCC, 2009)

CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC. - Saiyu Ren; Ray Siferd (ITNG, 2011)

Passive component stacking to aid power supply decoupling. - Christopher Benedik; Saiyu Ren (MWSCAS, 2013)

Design and implementation of a 16-bit flexible ROM-less direct digital synthesizer. - Sunny Raj Dommaraju; Saiyu Ren; George Y. Lee (MWSCAS, 2013)

Digital Down Converter optimization. - Joe Gerhardt; Saiyu Ren (MWSCAS, 2013)

FPGA design space exploration of IDEA cryptography IP core. - Dinesh Varma Penumetcha; Jiafeng Xie; Saiyu Ren (MWSCAS, 2015)

A 1.1-8.2 GHz tuning range In-phase and Quadrature output DCO design in 90 nm CMOS technology. - Eswar Raju Suraparaju; Pushpak Vasanth Rayudu Arja; Saiyu Ren (MWSCAS, 2015)

A 1-6 GHz analog radio frequency power driver in 90 nm complementary metal-oxide semiconductor technology for wireless applications. - Saiyu Ren; Isaac Abraham; Seng Hong (Int. J. Circuit Theory Appl., 2015)

A Low-Power and Area-Efficient 64-Bit Digital Comparator. - N. V. Vijaya Krishna Boppana; Saiyu Ren (J. Circuits Syst. Comput., 2016)

High Frequency Unity Gain Buffer in 90-nm CMOS Technology. - Shuo Li; Xiaomeng Zhang; Saiyu Ren (J. Circuits Syst. Comput., 2016)

Hardware Trojan detection by timing measurement: Theory and implementation. - Hao Xue; Saiyu Ren (Microelectron. J., 2018)

Memristor based multifunction oscillator. - Isaac Abraham; Saiyu Ren (MWSCAS, 2019)

Logistic Function Based Memristor Model With Circuit Application. - Isaac Abraham; Saiyu Ren; Raymond E. Siferd (IEEE Access, 2019)

Low-Cost and High-Performance 8 × 8 Booth Multiplier. - N. V. Vijaya Krishna Boppana; Jeevani Kommareddy; Saiyu Ren (Circuits Syst. Signal Process., 2019)

A 170 MHz to 330 MHz Wideband 90 nm CMOS RC-CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver. - Xiaomeng Zhang; Shuo Li; Ray Siferd; Saiyu Ren (Circuits Syst. Signal Process., 2021)