An expandable topology with low wiring congestion for silicon interposer-based network-on-chip systems. - Sajed Dadashi; Midia Reshadi; Akram Reza; Ahmad Khademzadeh (Trans. Emerg. Telecommun. Technol., 2019)

Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip. - Sajed Dadashi; Akram Reza; Midia Reshadi; Ahmad Khademzadeh (J. Supercomput., 2019)