An efficient approach for designing and minimizing reversible programmable logic arrays. - Sajib Kumar Mitra; Lafifa Jamal; Mineo Kaneko; Hafiz Md. Hasan Babu (ACM Great Lakes Symposium on VLSI, 2012)

Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis. - Sajib Kumar Mitra; Ahsan Raja Chowdhury (VLSI Design, 2012)

Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis. - Sajib Kumar Mitra; Ahsan Raja Chowdhury (VLSID, 2015)

On the Analysis of Reversible Booth's Multiplier. - Jakia Sultana; Sajib Kumar Mitra; Ahsan Raja Chowdhury (VLSID, 2015)