Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays. - Sami Khawam; Sajid Baloch; Arjun Pai; Imran Ahmed 001; Nizamettin Aydin; Tughrul Arslan; Fred Westall (DATE, 2004)

Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications. - Sajid Baloch; Imran Ahmed 001; Tughrul Arslan; Adrian Stoica (FPL, 2005)

Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication. - Imran Ahmed 001; Tughrul Arslan; Sajid Baloch; Ian Underwood; Robin Woodburn (IPDPS, 2005)

Domain-Specific Reconfigurable Array Targeting Discrete Wavelet Transform for System-on-Chip Applications. - Sajid Baloch; Imran Ahmed 001; Tughrul Arslan (IPDPS, 2005)

Improved memory strategy for logmap turbo decoders. - Imran Ahmed 001; Tughrul Arslan; Sajid Baloch (SoCC, 2005)

Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques. - Sajid Baloch; Tughrul Arslan; Adrian Stoica (AHS, 2006)

An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures. - Sajid Baloch; Tughrul Arslan; Adrian Stoica (AHS, 2006)

An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures. - Sajid Baloch; Tughrul Arslan; Adrian Stoica (FPL, 2006)

Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices. - Sajid Baloch; Tughrul Arslan; Adrian Stoica (ISQED, 2006)

Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications. - Sajid Baloch; Tughrul Arslan; Adrian Stoica (IPDPS, 2007)

Single event upset hardened embedded domain specific reconfigurable architecture. - Sajid Baloch (2007)

Hardware realization of locally normalized cross correlation algorithm. - Sajid Baloch; Fahad Al Ghazali; N. Mir; Fasih Ud Din Farrukh; H. Ismail; Muhammad Yasir Qadri (ICSAI, 2014)

An Integer Cat Swarm Optimization Approach for Energy and Throughput Efficient MPSoC Design. - Shahid Ali Murtza; Ayaz Ahmad; Muhammad Yasir Qadri; Nadia N. Qadri; Majed Alhaisoni; Sajid Baloch (Int. J. Comput. Intell. Syst., 2020)

FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism. - Muhammad Kashif Minhas; Haroon Waris; Sajid Baloch (VLSI-SoC, 2024)