A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. - Jai Gopal Pandey; Tarun Goel; Mausam Nayak; Chhavi Mitharwal; Sajid Khan 001; Santosh Kumar Vishvakarma; Abhijit Karmakar; Raj Singh (VDAT, 2018)

Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell. - Neha Gupta; Tanisha Gupta; Sajid Khan 001; Abhinav Vishwakarma; Santosh Kumar Vishvakarma (VDAT, 2019)

An Ultra Low Power AES Architecture for IoT. - Sajid Khan 001; Neha Gupta; Gopal Raut; Gunjan Rajput; Jai Gopal Pandey; Santosh Kumar Vishvakarma (VDAT, 2019)

Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. - Sajid Khan 001; Neha Gupta; Abhinav Vishwakarma; Shailesh Singh Chouhan; Jai Gopal Pandey; Santosh Kumar Vishvakarma (VDAT, 2019)

Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. - Gopal Raut; Vishal Bhartiy; Gunjan Rajput; Sajid Khan 001; Ankur Beohar; Santosh Kumar Vishvakarma (VDAT, 2019)

An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. - Sajid Khan 001; Ambika Prasad Shah; Neha Gupta; Shailesh Singh Chouhan; Jai Gopal Pandey; Santosh Kumar Vishvakarma (Microelectron. J., 2019)

Pass Transistor XOR Gate Based Radiation Hardened RO-PUF. - Syed Farah Naz; Sajid Khan 001; Ambika Prasad Shah (VDAT, 2022)