Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits. - Mustafa Altun; Sajjad Parvin; M. Hüsrev Cilasun (IEEE Access, 2018)

Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates. - Sajjad Parvin; Mustafa Altun (IOLTS, 2019)

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates. - Sajjad Parvin; Mustafa Altun (IEEE Access, 2019)

Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks. - Levent Aksoy; Sajjad Parvin; Mohammadreza Esmali Nojehdeh; Mustafa Altun (ISCAS, 2020)

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. - Mohammadreza Esmali Nojehdeh; Sajjad Parvin; Mustafa Altun (ISVLSI, 2021)

A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks. - Sajjad Parvin; Mustafa Altun (ISVLSI, 2021)

Efficient Hardware Realizations of Feedforward Artificial Neural Networks. - Mohammadreza Esmali Nojehdeh; Sajjad Parvin; Mustafa Altun (CoRR, 2021)

Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. - Sajjad Parvin; Thilo Krachenfels; Shahin Tajik; Jean-Pierre Seifert; Frank Sill Torres; Rolf Drechsler (ASP-DAC, 2022)

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. - Sajjad Parvin; Mehran Goli; Frank Sill Torres; Rolf Drechsler (ASP-DAC, 2023)

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. - Sajjad Parvin; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (COINS, 2023)

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. - Sajjad Parvin; Mehran Goli; Frank Sill Torres; Rolf Drechsler (DATE, 2023)

LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. - Sajjad Parvin; Mehran Goli; Thilo Krachenfels; Shahin Tajik; Jean-Pierre Seifert; Frank Sill Torres; Rolf Drechsler (ISVLSI, 2023)

Hidden Cost of Circuit Design with RFETs. - Sajjad Parvin; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (DATE, 2024)

Lower the RISC: Designing optical-probing-attack-resistant cores. - Sajjad Parvin; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (Microprocess. Microsystems, 2024)

True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET. - Sajjad Parvin; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (VLSID, 2025)

OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files. - Sajjad Parvin; Mehran Goli; Frank Sill Torres; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Auto-OPS: A Framework for Automated Optical Probing Simulation on GDS-II. - Paul Flammarion; Sajjad Parvin; Frank Sill Torres; Rolf Drechsler (IEEE Embed. Syst. Lett., 2025)

FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits. - Sallar Ahmadi-Pour; Sajjad Parvin; Chandan Kumar Jha 001; Rolf Drechsler (ACM Trans. Design Autom. Electr. Syst., 2025)