Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications. - Raed Bani-Hani; Khaldoon Mhaidat; Salah S. Harb (J. Circuits Syst. Comput., 2016)

Accelerating Square Root Computations Over Large GF (2m). - Salah S. Harb; Moath H. A. Jarrah (SECRYPT, 2017)

Time and Space-Efficient Write Parallelism in PCM by Exploiting Data Patterns. - Zheng Li 005; Fang Wang 001; Dan Feng 001; Yu Hua 001; Jingning Liu; Wei Tong 001; Yu Chen; Salah S. Harb (IEEE Trans. Computers, 2017)

High-performance Pipelined FPGA Implementation of the Elliptic Curve Cryptography over GF (2n). - Salah S. Harb; M. Omair Ahmad; M. N. S. Swamy (ICETE (2), 2019)

A Reconfigurable Implementation of Elliptic Curve Cryptography over GF (2n). - Salah S. Harb; M. Omair Ahmad; M. N. S. Swamy (ICETE (Selected Papers), 2019)

FPGA Implementation of the ECC Over GF(2m) for Small Embedded Applications. - Salah S. Harb; Moath H. A. Jarrah (ACM Trans. Embed. Comput. Syst., 2019)

Design and Hardware Implementation of a Separable Image Steganographic Scheme Using Public-key Cryptosystem. - Salah S. Harb; M. Omair Ahmad; M. N. S. Swamy (CoRR, 2020)

An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform. - Salah S. Harb; M. Omair Ahmad; M. N. S. Swamy (J. Real Time Image Process., 2023)

High-Speed Pipelined FPGA Implementation of a Robust Steganographic Scheme for Secure Data Communication Systems. - Salah S. Harb; M. Omair Ahmad; M. N. S. Swamy (SECRYPT, 2024)