A VLSI High-Performance Priority Encoder Using Standard CMOS Library. - Saleh Abdel-Hafeez; Shadi M. Harb (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. - Saleh Abdel-Hafeez; Shadi M. Harb; William R. Eisenstadt (PATMOS, 2007)

A low-power CAM using a 12-transistor design cell. - Saleh Abdel-Hafeez; Shadi M. Harb; William R. Eisenstadt (VLSI-SoC, 2007)

High speed digital CMOS divide-by-N fequency divider. - Saleh Abdel-Hafeez; Shadi M. Harb; William R. Eisenstadt (ISCAS, 2008)

CMOS Eight-Transistor Memory Cell for Low-Dynamic-Power High-Speed Embedded SRAM. - Saleh Abdel-Hafeez; Anas S. Matalkah (J. Circuits Syst. Comput., 2008)

A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure. - Saleh Abdel-Hafeez; Ann Gordon-Ross (Circuits Syst. Signal Process., 2011)

A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter. - Saleh Abdel-Hafeez; Ann Gordon-Ross; Asem Albosul; Ahmad Shatnawi; Shadi M. Harb (Informatica (Slovenia), 2011)

A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic. - Saleh Abdel-Hafeez; Ann Gordon-Ross (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A double data rate 8T-cell SRAM architecture for systems-on-chip. - Saleh Abdel-Hafeez; Mohammad Shatnawi; Ann Gordon-Ross (ISSoC, 2012)

Scalable Digital CMOS Comparator Using a Parallel Prefix Tree. - Saleh Abdel-Hafeez; Ann Gordon-Ross; Behrooz Parhami (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An Efficient O(N) Comparison-Free Sorting Algorithm. - Saleh Abdel-Hafeez; Ann Gordon-Ross (IEEE Trans. Very Large Scale Integr. Syst., 2017)

High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder. - Saleh Abdel-Hafeez; Ali M. Shatnawi (Circuits Syst. Signal Process., 2018)

A comparison-free sorting algorithm on CPUs and GPUs. - Saleh Abdel-Hafeez; Ann Gordon-Ross; Samer Abubaker (J. Supercomput., 2018)

A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems. - Ann Gordon-Ross; Saleh Abdel-Hafeez; Mohamad Hammam Alsafrjalani (ISVLSI, 2019)

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication. - Saleh Abdel-Hafeez; Ann Gordon-Ross (Int. J. Circuit Theory Appl., 2021)

Design of memory Alias Table based on the SRAM 8T-Cell. - Saleh Abdel-Hafeez; Sanabel Otoom; Muhannad Quwaider (Int. J. Circuit Theory Appl., 2022)

A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems. - Saleh Abdel-Hafeez; Shadi M. Harb (IET Comput. Digit. Tech., 2023)

Programmable Feedback Shift Register. - Saleh Abdel-Hafeez (Circuits Syst. Signal Process., 2023)

A fast and cost-effective integer restoring division hardware. - Saleh Abdel-Hafeez (Comput. Electr. Eng., 2024)