A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. - Luigi Grimaldi; Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2019)

A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. - Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2019)

Jitter Minimization in Digital PLLs with Mid-Rise TDCs. - Luca Avallone; Michael Peter Kennedy; Saleh Karman; Carlo Samori; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Simone Mattia Dartizio; Abanob Shehata; Francesco Tesolin; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea Leonardo Lacaita; Michael Peter Kennedy; et al. (ISSCC, 2021)

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. - Alessio Santiccioli; Mario Mercandelli; Simone Mattia Dartizio; Francesco Tesolin; Saleh Karman; Abanob Shehata; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; et al. (ISSCC, 2021)

A Novel Topology of Coupled Phase-Locked Loops. - Saleh Karman; Francesco Tesolin; Salvatore Levantino; Carlo Samori (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Multi-core frequency synthesizers for MM-wave communications. - Saleh Karman (2021)

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. - Simone Mattia Dartizio; Francesco Tesolin; Mario Mercandelli; Alessio Santiccioli; Abanob Shehata; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea L. Lacaita; Michael Peter Kennedy; et al. (IEEE J. Solid State Circuits, 2022)

34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS. - Simone Mattia Dartizio; Giacomo Castoro; Stefano Gallucci; Michele Rossoni; Riccardo Moleri; Francesco Tesolin; Pietro Salvi; Saleh Karman; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2025)