An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines. - Ali El-Zein; Salim Chowdhury (ICCAD, 1992)

Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections. - Monjurul Haque; Salim Chowdhury (DAC, 1993)

Maximum crosstalk in a transmission line system with linear time-invariant terminal networks. - Ali El-Zein; Salim Chowdhury (ISCAS, 1993)

A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections. - Monjurul Haque; Ali El-Zein; Salim Chowdhury (DAC, 1994)

Simulating Uniform Lossy Lines by the Time-Domain Modal Analysis. - Ali El-Zein; Monjurul Haque; Salim Chowdhury (ICCD, 1994)

Simulating Nonuniform Lossy Lines with Frequency Dependent Parameters by the Method of Characteristics. - Ali El-Zein; Monjurul Haque; Salim Chowdhury (ISCAS, 1994)

Transient Simulation of Nonuniform Transmission Lines by Asymptotic Waveform Evaluation. - Monjurul Haque; Ali El-Zein; Salim Chowdhury (ISCAS, 1994)

Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction. - Arani Sinha; Salim Chowdhury (CICC, 1999)

Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. - Salim Chowdhury; John Lillis (ISPD, 2007)

Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. - Yilin Zhang; Ashutosh Chakraborty; Salim Chowdhury; David Z. Pan (ICCAD, 2012)

BOB-router: A new buffering-aware global router with over-the-block routing resources optimization. - Yilin Zhang; Salim Chowdhury; David Z. Pan (ASP-DAC, 2014)

TILA: Timing-Driven Incremental Layer Assignment. - Bei Yu 001; Derong Liu 002; Salim Chowdhury; David Z. Pan (ICCAD, 2015)

Incremental layer assignment for critical path timing. - Derong Liu 002; Bei Yu 001; Salim Chowdhury; David Z. Pan (DAC, 2016)

Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. - Derong Liu 002; Vinicius S. Livramento; Salim Chowdhury; Duo Ding; Huy Vo; Akshay Sharma; David Z. Pan (DAC, 2017)

Incremental Layer Assignment Driven by an External Signoff Timing Engine. - Vinicius S. Livramento; Derong Liu 002; Salim Chowdhury; Bei Yu 001; Xiaoqing Xu; David Z. Pan; José Luís Almada Güntzel; Luiz C. V. dos Santos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Incremental Layer Assignment for Timing Optimization. - Derong Liu 002; Bei Yu 001; Salim Chowdhury; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2017)

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. - Derong Liu 002; Bei Yu 001; Salim Chowdhury; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. - Derong Liu 002; Bei Yu 001; Vinicius S. Livramento; Salim Chowdhury; Duo Ding; Huy Vo; Akshay Sharma; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)