On-chip Communication Buffer Architecture Optimization Considering Bus Width. - Salita Sombatsiri; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (MCSoC, 2012)

An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. - Salita Sombatsiri; Yoshinori Takeuchi; Masaharu Imai (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA. - Salita Sombatsiri; Seiya Shibata; Yuki Kobayashi; Hiroaki Inoue; Takashi Takenaka; Takeo Hosomi; Jaehoon Yu; Yoshinori Takeuchi (IPSJ Trans. Syst. LSI Des. Methodol., 2019)