Ultrasonic Wireless Sensor Network for Human Habitation in Deep Space Mission. - Hendra Kesuma; Sallar Ahmadi-Pour; Hans-Jürgen Zimmerman; Amber Joseph; Patrick Weis (WiSEE, 2019)

RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. - Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (FDL, 2021)

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. - Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (MBMV, 2021)

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. - Sallar Ahmadi-Pour; Sangeet Saha; Vladimir Herdt; Rolf Drechsler; Klaus D. McDonald-Maier (DSD, 2022)

The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. - Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (J. Syst. Archit., 2022)

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. - Sajjad Parvin; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (COINS, 2023)

Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. - Milan Funck; Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (FDL, 2023)

Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap. - Sallar Ahmadi-Pour; Pascal Pieper; Rolf Drechsler (CoRR, 2023)

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors. - Chandan Kumar Jha 001; Sallar Ahmadi-Pour; Rolf Drechsler (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Security Coverage Metrics for Information Flow at the System Level. - Ece Nur Demirhan Coskun; Sallar Ahmadi-Pour; Muhammad Hassan 002; Rolf Drechsler (ASPDAC, 2024)

LLMs for Hardware Verification: Frameworks, Techniques, and Future Directions. - Khushboo Qayyum; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Muhammad Hassan 002; Rolf Drechsler (ATS, 2024)

Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. - Khushboo Qayyum; Muhammad Hassan 002; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Rolf Drechsler (DAC, 2024)

LLM-Guided Formal Verification Coupled with Mutation Testing. - Muhammad Hassan 002; Sallar Ahmadi-Pour; Khushboo Qayyum; Chandan Kumar Jha 001; Rolf Drechsler (DATE, 2024)

Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study. - Mohammad Reza Heidari Iman; Sallar Ahmadi-Pour; Rolf Drechsler; Tara Ghasempouri (NorCAS, 2024)

Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. - Chandan Kumar Jha 001; Sallar Ahmadi-Pour; Rolf Drechsler (VLSID, 2024)

Lower the RISC: Designing optical-probing-attack-resistant cores. - Sajjad Parvin; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (Microprocess. Microsystems, 2024)

CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution. - Karl Aaron Rudkowski; Sallar Ahmadi-Pour; Rolf Drechsler (DDECS, 2025)

River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars. - Till Schnittka; Chandan Kumar Jha 001; Sallar Ahmadi-Pour; Rolf Drechsler (DDECS, 2025)

Large Language Models (LLMs) for Verification, Testing, and Design. - Chandan Kumar Jha 001; Muhammad Hassan 001; Khushboo Qayyum; Sallar Ahmadi-Pour; Kangwei Xu; Ruidi Qiu; Jason Blocklove; Luca Collini; Andre Nakkab; Ulf Schlichtmann; Grace Li Zhang; Ramesh Karri; et al. (ETS, 2025)

System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit. - Deepak Ravibabu; Sallar Ahmadi-Pour; Muhammad Hassan 002; Abhoy Kole; Chandan Kumar Jha 001; Rolf Drechsler (FDL, 2025)

MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems. - Sallar Ahmadi-Pour; Sangeet Saha; Klaus D. McDonald-Maier; Rolf Drechsler (ACM Trans. Design Autom. Electr. Syst., 2025)

FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits. - Sallar Ahmadi-Pour; Sajjad Parvin; Chandan Kumar Jha 001; Rolf Drechsler (ACM Trans. Design Autom. Electr. Syst., 2025)

Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution. - Karl Aaron Rudkowski; Sallar Ahmadi-Pour; Rolf Drechsler (CoRR, 2025)

LLM-assisted Bug Identification and Correction for Verilog HDL. - Khushboo Qayyum; Chandan Kumar Jha 001; Sallar Ahmadi-Pour; Muhammad Hassan 002; Rolf Drechsler (ACM Trans. Design Autom. Electr. Syst., 2025)