A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients. - Sally Safwat; Maged Ghoneima; Yehea I. Ismail (ICEAC, 2011)

A 12Gbps all digital low power SerDes transceiver for on-chip networking. - Sally Safwat; Ezz El-Din O. Hussein; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2011)

A 16Gbps low power self-timed SerDes transceiver for multi-core communication. - Ezz El-Din O. Hussein; Sally Safwat; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2012)

A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. - Sally Safwat; Amr Lotfy; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2012)

A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters. - Sally Safwat; Rinkle Jain; Dawson Kesling (ISCAS, 2014)