Re-engineering hardware specifications by exploiting design semantics. - Salvador Mir; Nick Filer (EURO-DAC, 1994)

Built-in self-test and fault diagnosis of fully differential analogue circuits. - Salvador Mir; Vladimir Kolarik; Marcelo Lubaszewski; C. Nielsen; Bernard Courtois (ICCAD, 1994)

Mixed-signal circuits and boards for high safety applications. - Marcelo Lubaszewski; Vladimir Kolarik; Salvador Mir; C. Nielsen; Bernard Courtois (ED&TC, 1995)

Analog checkers with absolute and relative tolerances. - Vladimir Kolarik; Salvador Mir; Marcelo Lubaszewski; Bernard Courtois (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits. - Salvador Mir; Bernard Courtois; Marcelo Lubaszewski; Vladimir Kolarik (ED&TC, 1996)

ABILBO: Analog BuILt-in Block Observer. - Marcelo Lubaszewski; Salvador Mir; Leandro Pulz (ICCAD, 1996)

Design of high-performance band-pass sigma-delta modulator with concurrent error detection. - Fabrizio Francesconi; Valentino Liberali; Marcelo Lubaszewski; Salvador Mir (ICECS, 1996)

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. - Salvador Mir; Marcelo Lubaszewski; Bernard Courtois (J. Electron. Test., 1996)

Unified built-in self-test for fully differential analog circuits. - Salvador Mir; Marcelo Lubaszewski; Bernard Courtois (J. Electron. Test., 1996)

SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. - Salvador Mir; Adoración Rueda; Thomas Olbrich; Eduardo J. Peralías; José Luis Huertas (DAC, 1997)

Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. - Salvador Mir; Adoración Rueda; Diego Vázquez; José Luis Huertas (DATE, 1998)

Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems. - A. Castillejo; D. Veychard; Salvador Mir; Jean-Michel Karam; Bernard Courtois (ITC, 1998)

A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. - Marcelo Lubaszewski; Michel Renovell; Salvador Mir; Florence Azaïs; Yves Bertrand (SBCCI, 1998)

Fault modeling of suspended thermal MEMS. - Benoît Charlot; Salvador Mir; Érika F. Cota; Marcelo Lubaszewski; Bernard Courtois (ITC, 1999)

Design and Test of MEMs. - Bernard Courtois; Jean-Michel Karam; Salvador Mir; Marcelo Lubaszewski; Vladimír Székely; Márta Rencz; Klaus Hofmann; Manfred Glesner (VLSI Design, 1999)

On the Integration of Design and Test for Chips Embedding MEMS. - Salvador Mir; Benoît Charlot (IEEE Des. Test Comput., 1999)

Towards design and validation of mixed-technology SOCs. - Salvador Mir; Benoît Charlot; Gabriela Nicolescu; Philippe Coste; Fabien Parrain; Nacer-Eddine Zergainoh; Bernard Courtois; Ahmed Amine Jerraya; Márta Rencz (ACM Great Lakes Symposium on VLSI, 2000)

Extending Fault-Based Testing to Microelectromechanical Systems. - Salvador Mir; Benoît Charlot; Bernard Courtois (J. Electron. Test., 2000)

Design of self-checking fully differential circuits and boards. - Marcelo Lubaszewski; Salvador Mir; Vladimir Kolarik; C. Nielsen; Bernard Courtois (IEEE Trans. Very Large Scale Integr. Syst., 2000)

An Analog-based Approach for MEMS Testing. - Bernard Courtois; Salvador Mir; Benoît Charlot; Marcelo Lubaszewski (LATW, 2001)

Electrically Induced Stimuli For MEMS Self-Test. - Benoît Charlot; Salvador Mir; Fabien Parrain; Bernard Courtois (VTS, 2001)

Generation of Electrically Induced Stimuli for MEMS Self-Test. - Benoît Charlot; Salvador Mir; Fabien Parrain; Bernard Courtois (J. Electron. Test., 2001)

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? - Salvador Mir; H. Bederr; R. D. (Shawn) Blanton; Hans G. Kerkhoff; H. J. Klim (VTS, 2002)

An implementation of memory-based on-chip analogue test signal generation. - Salvador Mir; Luís Rolíndez; Christian Domigues; Libor Rufer (ASP-DAC, 2003)

On-Line Testable Decimation Filter Design for AMS Systems. - Mohammad A. Naal; Emmanuel Simeu; Salvador Mir (IOLTS, 2003)

Building an analogue fault simulation tool and its application to MEMS. - Cosmin Roman; Salvador Mir; Benoît Charlot (Microelectron. J., 2003)

A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. - Luís Rolíndez; Salvador Mir; Guillaume Prenat; Ahcène Bounceur (DATE, 2004)

Mems built-in-self-test using MLS. - Achraf Dhayni; Salvador Mir; Libor Rufer (ETS, 2004)

On-chip testing of embedded silicon transducers. - Salvador Mir; Benoît Charlot; Libor Rufer; Bernard Courtois (SoCC, 2004)

On-chip testing of embedded transducers. - Salvador Mir; Libor Rufer; Bernard Courtois (VLSI Design, 2004)

Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. - Rabeb Kheriji; V. Danelon; Jean-Louis Carbonéro; Salvador Mir (DATE, 2005)

A built-in IDDQ testing circuit. - Sotirios Matakias; Yiorgos Tsiatouhas; Angela Arapoyanni; Th. Haniotakis; Guillaume Prenat; Salvador Mir (ESSCIRC, 2005)

Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities. - Achraf Dhayni; Salvador Mir; Libor Rufer (ETS, 2005)

On-chip Pseudorandom Testing for Linear and Nonlinear MEMS. - Achraf Dhayni; Salvador Mir; Libor Rufer; Ahcène Bounceur (VLSI-SoC, 2005)

On-Chip Pseudorandom MEMS Testing. - Libor Rufer; Salvador Mir; Emmanuel Simeu; C. Domingues (J. Electron. Test., 2005)

Analog and mixed signal test techniques for SOC development. - Bozena Kaminska; Stephen K. Sunter; Salvador Mir (Microelectron. J., 2005)

A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. - Guillaume Prenat; Salvador Mir; Diego Vázquez; Luís Rolíndez (Microelectron. J., 2005)

Pseudorandom functional BIST for linear and nonlinear MEMS. - Achraf Dhayni; Salvador Mir; Libor Rufer; Ahcène Bounceur (DATE, 2006)

CAT platform for analogue and mixed-signal test evaluation and optimization. - Ahcène Bounceur; Salvador Mir; Luís Rolíndez; Emmanuel Simeu (VLSI-SoC, 2006)

Study of a BIST Technique for CMOS Active Pixel Sensors. - Livier Lizarraga; Salvador Mir; Gilles Sicard; Ahcène Bounceur (VLSI-SoC, 2006)

A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. - Luís Rolíndez; Salvador Mir; Ahcène Bounceur; Jean-Louis Carbonéro (VTS, 2006)

Guest Editorial. - Salvador Mir; Kwang-Ting (Tim) Cheng; Andrew Richardson 001 (J. Electron. Test., 2006)

A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting. - Luís Rolíndez; Salvador Mir; Ahcène Bounceur; Jean-Louis Carbonéro (J. Electron. Test., 2006)

Built-in-self-test techniques for MEMS. - Salvador Mir; Libor Rufer; Achraf Dhayni (Microelectron. J., 2006)

Test Education in the Global Economy. - Jacob Abraham; Salvador Mir; Yinghua Min; Jeremy Wang; Cheng-Wen Wu (ATS, 2007)

Evaluation of a BIST Technique for CMOS Imagers. - Livier Lizarraga; Salvador Mir; Gilles Sicard (ATS, 2007)

Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. - Jeanne Tongbong; Salvador Mir; Jean-Louis Carbonéro (DATE, 2007)

Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. - Emmanuel Simeu; Salvador Mir; R. Kherreddine; Hoang Nam Nguyen (IOLTS, 2007)

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test. - Luís Rolíndez; Salvador Mir; Jean-Louis Carbonéro; Dimitri Goguet; Nabil Chouba (ITC, 2007)

Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing. - Ahcène Bounceur; Salvador Mir; Emmanuel Simeu; Luís Rolíndez (J. Electron. Test., 2007)

A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. - Haralampos-G. D. Stratigopoulos; Jeanne Tongbong; Salvador Mir (DATE, 2008)

Using Signal Envelope Detection for Online and Offline RF MEMS Switch Testing. - Emmanuel Simeu; Hoang Nam Nguyen; Philippe Cauvet; Salvador Mir; Libor Rufer; Rafik Khereddine (VLSI Design, 2008)

Enrichment of limited training sets in machine-learning-based analog/RF test. - Haralampos-G. D. Stratigopoulos; Salvador Mir; Yiorgos Makris (DATE, 2009)

Defect Filter for Alternate RF Test. - Haralampos-G. D. Stratigopoulos; Salvador Mir; Erkan Acar; Sule Ozev (ETS, 2009)

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study. - Matthieu Dubois; Haralampos-G. D. Stratigopoulos; Salvador Mir (ICCD, 2009)

Parameter identification of RF transceiver blocks using regressive models. - Rafik Khereddine; Emmanuel Simeu; Salvador Mir (PDeS, 2009)

Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors. - Livier Lizarraga; Salvador Mir; Gilles Sicard (VTS, 2009)

Pseudorandom BIST for test and characterization of linear and nonlinear MEMS. - Achraf Dhayni; Salvador Mir; Libor Rufer; Ahcène Bounceur; Emmanuel Simeu (Microelectron. J., 2009)

Evaluation of Analog/RF Test Measurements at the Design Stage. - Haralampos-G. D. Stratigopoulos; Salvador Mir; Ahcène Bounceur (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation. - Ke Huang 001; Haralampos-G. D. Stratigopoulos; Salvador Mir (Asian Test Symposium, 2010)

Fault diagnosis of analog circuits based on machine learning. - Ke Huang 001; Haralampos-G. D. Stratigopoulos; Salvador Mir (DATE, 2010)

Low Frequency Test for RF MEMS Switches. - Gustavo Pamplona Rehder; Salvador Mir; Libor Rufer; Emmanuel Simeu; Hoang Nam Nguyen (DELTA, 2010)

Sensors for built-in alternate RF test. - Louay Abdallah; Haralampos-G. D. Stratigopoulos; Christophe Kelma; Salvador Mir (ETS, 2010)

Analog test metrics estimates with PPM accuracy. - Haralampos-G. D. Stratigopoulos; Salvador Mir (ICCAD, 2010)

Adaptive logical control of RF LNA performances for efficient energy consumption. - Rafik Khereddine; Louay Abdallah; Emmanuel Simeu; Salvador Mir; Fabio Cenni (VLSI-SoC, 2010)

Ordering of analog specification tests based on parametric defect level estimation. - Nourredine Akkouche; Salvador Mir; Emmanuel Simeu (VTS, 2010)

Density estimation for analog/RF test problem solving. - Salvador Mir; Haralampos-G. D. Stratigopoulos; Ahcène Bounceur (VTS, 2010)

Design of a SAW-based chemical sensor with its microelectronics front-end interface. - Fabio Cenni; Jeremie Cazalbou; Salvador Mir; Libor Rufer (Microelectron. J., 2010)

On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study. - Alexios Spyronasios; Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir (Asian Test Symposium, 2011)

Implicit test of high-speed analog circuits using non-intrusive sensors. - Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir (ECCTD, 2011)

RF Front-End Test Using Built-in Sensors. - Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir; Christophe Kelma (IEEE Des. Test Comput., 2011)

Estimation of Analog Parametric Test Metrics Using Copulas. - Ahcène Bounceur; Salvador Mir; Haralampos-G. D. Stratigopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Testing RF circuits with true non-intrusive built-in sensors. - Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir; Josep Altet (DATE, 2012)

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Christophe Forel (ETS, 2012)

Accurate estimation of analog test metrics with extreme circuits. - Kamel Beznia; Ahcène Bounceur; Louay Abdallah; Ke Huang 001; Salvador Mir; Reinhardt Euler (ICECS, 2012)

Experiences with non-intrusive sensors for RF built-in test. - Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir; Christophe Kelma (ITC, 2012)

Analog/RF test ordering in the early stages of production testing. - Nourredine Akkouche; Salvador Mir; Emmanuel Simeu; Mustapha Slamani (VTS, 2012)

Adaptive Alternate Analog Test. - Haralampos-G. D. Stratigopoulos; Salvador Mir (IEEE Des. Test Comput., 2012)

Diagnosis of Local Spot Defects in Analog Circuits. - Ke Huang 001; Haralampos-G. D. Stratigopoulos; Salvador Mir; Camelia Hora; Yizi Xing; Bram Kruseman (IEEE Trans. Instrum. Meas., 2012)

Statistical modelling of analog circuits for test metrics computation. - Kamel Beznia; Ahcène Bounceur; Salvador Mir; Reinhardt Euler (DTIS, 2013)

Multivariate statistical techniques for analog parametric test metrics estimation. - Ke Huang 001; Haralampos-G. D. Stratigopoulos; Louay Abdallah; Salvador Mir; Ahcène Bounceur (DTIS, 2013)

Efficient minimization of test frequencies for linear analog circuits. - Mohand Bentobache; Ahcène Bounceur; Reinhardt Euler; Yann Kieffer; Salvador Mir (ETS, 2013)

True non-intrusive sensors for RF built-in test. - Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir (ITC, 2013)

Fault modeling and diagnosis for nanometric analog circuits. - Ke Huang 001; Haralampos-G. D. Stratigopoulos; Salvador Mir (ITC, 2013)

BIST of interconnection lines in the pixel matrix of CMOS imagers. - Richun Fei; Jocelyn Moreau; Salvador Mir (IWASI, 2013)

New techniques for selecting test frequencies for linear analog circuits. - Mohand Bentobache; Ahcène Bounceur; Reinhardt Euler; Yann Kieffer; Salvador Mir (VLSI-SoC, 2013)

Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods. - Mohand Bentobache; Ahcène Bounceur; Reinhardt Euler; Salvador Mir; Yann Kieffer (VLSI-SoC (Selected Papers), 2013)

Defect-oriented non-intrusive RF test using on-chip temperature sensors. - Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir; Josep Altet (VTS, 2013)

Reduced code linearity testing of pipeline adcs in the presence of noise. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Gerard Bret (VTS, 2013)

Reduced-Code Linearity Testing of Pipeline ADCs. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Gerard Bret (IEEE Des. Test, 2013)

On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. - Guillaume Renaud; Manuel J. Barragán; Salvador Mir; Marc Sabut (ATS, 2014)

Low-cost EVM built-in test of RF transceivers. - Ayssar Serhan; Louay Abdallah; Haralampos-G. D. Stratigopoulos; Salvador Mir (IDT, 2014)

Solutions for the self-adaptation of communicating systems in operation. - Martin Andraud; Anthony Deluthault; Mouhamadou Dieng; Florence Azaïs; Serge Bernard; Philippe Cauvet; Mariane Comte; Thibault Kervaon; Vincent Kerzerho; Salvador Mir; Paul-Henri Pugliesi-Conti; Michel Renovell; et al. (IOLTS, 2014)

Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. - Josep Altet; Eduardo Aldrete-Vidrio; Ferran Reverter; Didac Gómez; José Luis González 001; Marvin Onabajo; José Silva-Martínez; B. Martineau; X. Perpiñà; Louay Abdallah; Haralampos-G. D. Stratigopoulos; Xavier Aragonès; et al. (MWSCAS, 2014)

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. - Matthieu Dubois; Haralampos-G. D. Stratigopoulos; Salvador Mir; Manuel J. Barragán (VLSI-SoC, 2014)

Statistical Evaluation of Digital Techniques for $ sum varDelta$ ADC BIST. - Matthieu Dubois; Haralampos-G. D. Stratigopoulos; Salvador Mir; Manuel J. Barragán (VLSI-SoC (Selected Papers), 2014)

High frequency jitter estimator for SoCs. - Hervé Le Gall; Rshdee Alhakim; Miroslav Valka; Salvador Mir; Haralampos-G. D. Stratigopoulos; Emmanuel Simeu (ETS, 2015)

Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors. - Athanasios Dimakos; Martin Andraud; Louay Abdallah; Haralampos-G. D. Stratigopoulos; Emmanuel Simeu; Salvador Mir (ISVLSI, 2015)

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. - Haralampos-G. D. Stratigopoulos; Manuel J. Barragán; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (ITC, 2015)

Horizontal-FPN fault coverage improvement in production test of CMOS imagers. - Richun Fei; Jocelyn Moreau; Salvador Mir; Alexis Marcellin; C. Mandier; E. Huss; G. Palmigiani; P. Vitrou; Thomas Droniou (VTS, 2015)

Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors. - Athanasios Dimakos; Haralampos-G. D. Stratigopoulos; Alexandre Siligaris; Salvador Mir; Emeric de Foucauld (J. Electron. Test., 2015)

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters. - Kamel Beznia; Ahcène Bounceur; Reinhardt Euler; Salvador Mir (ACM Trans. Design Autom. Electr. Syst., 2015)

Built-in test of millimeter-Wave circuits based on non-intrusive sensors. - Athanasios Dimakos; Haralampos-G. D. Stratigopoulos; Alexandre Siligaris; Salvador Mir; Emeric de Foucauld (DATE, 2016)

ADC Techniques for Optimized Conversion Time in CMOS Image Sensors. - Cédric Pastorelli; Pascal Mellot; Salvador Mir; Cédric Tubert (IMSE, 2016)

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. - Antonio J. Ginés; Eduardo J. Peralías; Gildas Léger; Adoración Rueda; Guillaume Renaud; Manuel J. Barragán; Salvador Mir (ETS, 2016)

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. - Manuel J. Barragán; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Des. Test, 2016)

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. - Guillaume Renaud; Manuel J. Barragán; Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Hervé Naudet (J. Electron. Test., 2016)

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. - Manuel J. Barragán; Rshdee Alhakim; Haralampos-G. D. Stratigopoulos; Matthieu Dubois; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. - Hani Malloug; Manuel J. Barragan Asian; Salvador Mir; Laurent Basteres; Hervé Le Gall (ETS, 2017)

Mixed-signal BIST computation offloading using IEEE 1687. - Michele Portolan; Manuel J. Barragán; Rshdee Alhakim; Salvador Mir (ETS, 2017)

Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. - Guillaume Renaud; Marc Margalef-Rovira; Manuel J. Barragán; Salvador Mir (VTS, 2017)

Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. - Florent Cilici; Manuel J. Barragán; Salvador Mir; Estelle Lauga-Larroze; Sylvain Bourdel (ETS, 2018)

Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. - Renato S. Feitoza; Manuel J. Barragán; Salvador Mir; Daniel Dzahini (IOLTS, 2018)

Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. - Hani Malloug; Manuel J. Barragán; Salvador Mir (J. Electron. Test., 2018)

On the use of causal feature selection in the context of machine-learning indirect test. - Manuel J. Barragán; Gildas Léger; Florent Cilici; Estelle Lauga-Larroze; Sylvain Bourdel; Salvador Mir (DATE, 2019)

A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. - Hani Malloug; Manuel J. Barragán; Salvador Mir (ETS, 2019)

Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. - Florent Cilici; Manuel J. Barragán; Salvador Mir; Estelle Lauga-Larroze; Sylvain Bourdel; Gildas Léger (ISCAS, 2019)

Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. - Florent Cilici; Gildas Léger; Manuel J. Barragán; Salvador Mir; Estelle Lauga-Larroze; Sylvain Bourdel (SMACD, 2019)

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. - Renato S. Feitoza; Manuel J. Barragán; Salvador Mir (VLSI-SoC, 2019)

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. - Guillaume Renaud; Mamadou Diallo; Manuel J. Barragán; Salvador Mir (IEEE Trans. Very Large Scale Integr. Syst., 2019)

On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter. - Renato S. Feitoza; Manuel J. Barragán; Antonio J. Ginés; Salvador Mir (ETS, 2020)

A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. - Michele Portolan; R. Silveira Feitoza; Ghislain Takam Tchendjou; Vincent Reynaud; Kalpana Senthamarai Kannan; Manuel J. Barragán; Emmanuel Simeu; Paolo Maistri; Lorena Anghel; Régis Leveugle; Salvador Mir (IOLTS, 2020)

Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique. - Renato S. Feitoza; Manuel J. Barragán; Antonio J. Ginés; Salvador Mir (NEWCAS, 2020)

Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model. - Ahcène Bounceur; Salvador Mir; Reinhardt Euler; Kamel Beznia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. - Ankush Mamgain; Manuel J. Barragán; Salvador Mir (ETS, 2021)

On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. - Ankush Mamgain; Salvador Mir; Jai Narayan Tripathi; Manuel J. Barragán (ATS, 2022)

Special Session on RF/5G Test. - William R. Eisenstadt; Mark Roos; Devin Morris; José Luis González-Jiménez; Christopery Mounet; Manuel J. Barragán; Gildas Léger; Florent Cilici; Estelle Lauga-Larroze; Salvador Mir; Sylvain Bourdel; Marc Margalef-Rovira; et al. (ETS, 2022)

A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. - Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán (VLSI-SoC, 2022)

Innovative Practices Track: Innovative Analog Circuit Testing Technologies. - Chris Mangelsdorf; Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán; Daisuke Iimori; Takayuki Nakatani; Shogo Katayama; Gaku Ogihara; Yujie Zhao; Jianglin Wei; Anna Kuwana; Kentaroh Katoh; et al. (VTS, 2022)

A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. - Ankush Mamgain; Salvador Mir; Jai Narayan Tripathi; Manuel J. Barragán (ISCAS, 2023)

Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. - Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán (LATS, 2023)

Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. - Ankush Mamgain; Salvador Mir; Jai Narayan Tripathi; Manuel J. Barragán (LATS, 2023)

A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA. - Ankush Mamgain; Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán; Jai Narayan Tripathi (NEWCAS, 2023)

Noise modeling using look-up tables and DC measurements for cryogenic applications. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Quentin Berlingard; Mikaël Cassé; Philippe Galy (VLSI-SoC, 2023)

An Integrated Miniaturized VNA for On-Chip PA Mismatch Measurement. - Oumayma Belkhadra; Gilles Montoriol; Emmanuel Pistone; Hugo Vallee; Florent Cilici; Manuel J. Barragán; Salvador Mir; Sylvain Bourdel (NewCAS, 2024)

LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Jose Lugo; Joao Azevedo; Sebastien Sadlo; Quentin Berlingard; Mikaël Cassé; Philippe Galy (NewCAS, 2024)

28 nm FD-SOI 4 K RF LNA Design Using DC Transistor Characterization Measurements. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Jose Lugo; Joao Azevedo; Sebastien Sadlo; Quentin Berlingard; Mickael Casse; Philippe Galy (LATS, 2025)